Abstract: An energy storage system includes a pair of rack frames spaced apart from each other and arranged side by side; a plurality of L brackets fastened to the rack frames; a plurality of battery modules respectively placed on a pair of L brackets facing each other to form a plurality of layers along a longitudinal direction of the rack frame; a first heat transfer member interposed between the battery module and the L bracket; and a second heat transfer member interposed between the rack frame and the L bracket.

Abstract: Disclosed is a method and apparatus for testing an internal short of a secondary battery by simulating the use environment situation where the secondary battery is actually used, and a secondary battery for an internal short test, which is used in the method. The method for testing an internal short of a secondary battery includes the steps of mounting a P-N junction diode in a secondary battery; charging the secondary battery; and evaluating a state of the secondary battery by considering that an internal short occurs in the secondary battery when the P-N junction diode is switched on.

Abstract: A battery module includes a unit module stack formed by stacking a plurality of unit modules, each unit module having a plurality of battery cells stacked on each other; a swelling absorption pad interposed between the unit modules adjacent to each other; and a module housing configured to accommodate the unit module stack and the swelling absorption pad, wherein the swelling absorption pad has a coolant channel formed to extend along a longitudinal direction thereof.

Abstract: A battery module includes a unit module stack formed by stacking a plurality of unit modules, each unit module having a plurality of battery cells stacked on each other; a swelling absorption pad interposed between the unit modules adjacent to each other; and a module housing configured to accommodate the unit module stack and the swelling absorption pad, wherein the swelling absorption pad has a coolant channel formed to extend along a longitudinal direction thereof.

Abstract: A battery module includes module case having a heatsink mounted to at least one side thereof. A plurality of battery cells are accommodated in the module case and stacked to be electrically connected to each other, and a plurality of pores are formed between facing battery cells among the plurality of battery cells to delay heat transfer.

Abstract: An energy storage system includes a pair of rack frames spaced apart from each other and arranged side by side; a plurality of L brackets fastened to the rack frames; a plurality of battery modules respectively placed on a pair of L brackets facing each other to form a plurality of layers along a longitudinal direction of the rack frame; a first heat transfer member interposed between the battery module and the L bracket; and a second heat transfer member interposed between the rack frame and the L bracket.

Abstract: Disclosed is a method and apparatus for testing an internal short of a secondary battery by simulating the use environment situation where the secondary battery is actually used, and a secondary battery for an internal short test, which is used in the method. The method for testing an internal short of a secondary battery includes the steps of mounting a P-N junction diode in a secondary battery; charging the secondary battery; and evaluating a state of the secondary battery by considering that an internal short occurs in the secondary battery when the P-N junction diode is switched on.

Abstract: A non-volatile memory device including a cell array having memory cells arranged at intersections of word lines and bit lines; an address decoder configured to select one of the word lines in response to an address; a write circuit configured to write program data in memory cells connected with the selected word line; and a control circuit configured to control the address decoder and the write circuit such that a plurality of band program (write) operations are sequentially executed during a write operation, wherein the control circuit is further configured to select each band write operation the optimal write condition of the next band write operation. A plurality of available write conditions are stored as trim information in a plurality of registers. The control circuit selects the register storing information for performing programming under the optimal write condition.

Abstract: A non-volatile memory device including a cell array having memory cells arranged at intersections of word lines and bit lines; an address decoder configured to select one of the word lines in response to an address; a write circuit configured to write program data in memory cells connected with the selected word line; and a control circuit configured to control the address decoder and the write circuit such that a plurality of band program (write) operations are sequentially executed during a write operation, wherein the control circuit is further configured to select each band write operation the optimal write condition of the next band write operation. A plurality of available write conditions are stored as trim information in a plurality of registers. The control circuit selects the register storing information for performing programming under the optimal write condition.

Abstract: Nonvolatile memory devices support programming and verify operations that improve threshold-voltage distribution within programmed memory cells. This improvement is achieved by reducing a magnitude of the programming voltage steps and increasing a duration of the verify operations once at least one of the plurality of memory cells undergoing programming has been verified as a “passed” memory cell. The nonvolatile memory device includes an array of nonvolatile memory cells and a control circuit, which is electrically coupled to the array of nonvolatile memory cells. The control circuit is configured to perform a plurality of memory programming operations (P) by driving a selected word line in the array with a first stair step sequence of program voltages having first step height (e.g.

Abstract: A flash memory device includes a memory cell array and a multi-buffer block which temporarily stores program data that are to be stored in the memory cell array, wherein the multi-buffer block includes a plurality of buffer circuits which store at least 2-word data, respectively. Each of the buffer circuits includes a plurality of registers which store two corresponding data bits among the at least 2-word data, respectively and scan logics corresponding to the registers, respectively, which scan a number of program data of a first word data among the at least 2-word data during a first scan interval, and which scan a number of program data of a second word data among the at least 2-word data based on the number of the program data of the first word data during a second scan interval.

Abstract: Nonvolatile memory devices support programming and verify operations that improve threshold-voltage distribution within programmed memory cells. This improvement is achieved by reducing a magnitude of the programming voltage steps and increasing a duration of the verify operations once at least one of the plurality of memory cells undergoing programming has been verified as a “passed” memory cell. The nonvolatile memory device includes an array of nonvolatile memory cells and a control circuit, which is electrically coupled to the array of nonvolatile memory cells. The control circuit is configured to perform a plurality of memory programming operations (P) by driving a selected word line in the array with a first stair step sequence of program voltages having first step height (e.g.

Abstract: Nonvolatile memory devices support programming and verify operations that improve threshold-voltage distribution within programmed memory cells. This improvement is achieved by reducing a magnitude of the programming voltage steps and increasing a duration of the verify operations once at least one of the plurality of memory cells undergoing programming has been verified as a “passed” memory cell. The nonvolatile memory device includes an array of nonvolatile memory cells and a control circuit, which is electrically coupled to the array of nonvolatile memory cells. The control circuit is configured to perform a plurality of memory programming operations (P) by driving a selected word line in the array with a first stair step sequence of program voltages having first step height (e.g.

Abstract: Exposure equipment adapted for use in the manufacture of semiconductor devices and a related control are disclosed. A wafer stage in the exposure equipment comprises an image sensor adapted to detect patterned light from the reticle. Image data corresponding to the detected patterned light is compared to reference image data to verify a state of overlay mismatch of reticle pattern accuracy prior to wafer exposure.

Abstract: A flash memory device comprises a memory cell array and a multi-buffer block which temporarily stores program data that are to be stored in the memory cell array, wherein the multi-buffer block includes a plurality of buffer circuits which store at least 2-word data, respectively. Each of the buffer circuits comprises a plurality of registers which store two corresponding data bits among the at least 2-word data, respectively and scan logics corresponding to the registers, respectively, which scan a number of program data of a first word data among the at least 2-word data during a first scan interval, and which scan a number of program data of a second word data among the at least 2-word data based on the number of the program data of the first word data during a second scan interval.

Abstract: Nonvolatile memory devices support programming and verify operations that improve threshold-voltage distribution within programmed memory cells. This improvement is achieved by reducing a magnitude of the programming voltage steps and increasing a duration of the verify operations once at least one of the plurality of memory cells undergoing programming has been verified as a “passed” memory cell. The nonvolatile memory device includes an array of nonvolatile memory cells and a control circuit, which is electrically coupled to the array of nonvolatile memory cells. The control circuit is configured to perform a plurality of memory programming operations (P) by driving a selected word line in the array with a first stair step sequence of program voltages having first step height (e.g.

Abstract: Exposure equipment adapted for use in the manufacture of semiconductor devices and a related control are disclosed. A wafer stage in the exposure equipment comprises an image sensor adapted to detect patterned light from the reticle. Image data corresponding to the detected patterned light is compared to reference image data to verify a state of overlay mismatch of reticle pattern accuracy prior to wafer exposure.