Patents by Inventor Soojae Park
Soojae Park has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240021663Abstract: A wire capacitor includes a wire structure extending in a longitudinal direction and a conductive layer covering an outer surface of the wire structure. The wire structure includes a core electrode line having a wire shape and extending in the longitudinal direction and a dielectric line surrounding an outer surface of the core electrode line and extending in the longitudinal direction. The wire structure has a first end and a second end which are opposite to each other in the longitudinal direction, and the conductive layer exposes an outer circumference of the first end and the second end of the wire structure.Type: ApplicationFiled: June 23, 2023Publication date: January 18, 2024Applicant: Samsung Electronics Co., Ltd.Inventors: SOOJAE PARK, NAMHOON KIM, JONGHYUN LEE, CHUL-HYUNG CHO
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Publication number: 20240006122Abstract: Disclosed are capacitor wires and electronic devices including the same. The capacitor wire comprises a core electrode line having a wire shape extending in a length direction, an outer electrode line that covers at least a portion of the core electrode line and extends in the length direction of the core electrode line, and a dielectric line between the core electrode line and the outer electrode line and extending in the length direction of the core electrode line. The dielectric line has a porous structure including a plurality of holes.Type: ApplicationFiled: February 20, 2023Publication date: January 4, 2024Inventor: SOOJAE PARK
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Publication number: 20230319998Abstract: A wiring board includes an insulating layer having a first surface and a second surface, which are opposite to each other, upper wiring patterns on the first surface of the insulating layer, lower wiring patterns on the second surface of the insulating layer, intermediate wiring patterns, which are disposed in the insulating layer and are electrically connected to the upper wiring patterns and the lower wiring patterns, and a capacitor wire connected to corresponding wiring patterns of the upper wiring patterns, the lower wiring patterns, and the intermediate wiring patterns. The capacitor wire includes a core electrode line having a wire shape, an outer electrode line covering at least a portion of the core electrode line, and a dielectric line interposed between the core electrode line and the outer electrode line.Type: ApplicationFiled: November 7, 2022Publication date: October 5, 2023Inventor: SOOJAE PARK
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Publication number: 20230307180Abstract: A chip capacitor includes a substrate, a plurality of capacitor wires on the substrate, and a mold layer disposed on the substrate to cover the capacitor wires. Each of the capacitor wires includes a core electrode line having a wire shape, an outer electrode line covering at least a portion of the core electrode line, and a dielectric line interposed between the core electrode line and the outer electrode line.Type: ApplicationFiled: November 18, 2022Publication date: September 28, 2023Inventor: SOOJAE PARK
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Publication number: 20230245828Abstract: A capacitor wire includes a core electrode line provided in the form of a wire, an outer electrode line covering at least a portion of the core electrode line, and a dielectric line interposed between the core electrode line and the outer electrode line. The outer electrode line comprises material having a melting point lower than material of the core electrode line.Type: ApplicationFiled: September 8, 2022Publication date: August 3, 2023Inventor: SOOJAE PARK
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Patent number: 11508681Abstract: A semiconductor package includes a semiconductor substrate, a conductive pad on the semiconductor substrate, a redistribution line conductor, a coating insulator, and an aluminum oxide layer. The redistribution line conductor is electrically connected to the conductive pad. The coating insulator covers the redistribution line conductor and partially exposes the redistribution line conductor. The aluminum oxide layer is provided below the coating insulator and extends along a top surface of the redistribution line conductor, and the aluminum oxide layer is in contact with the redistribution line conductor.Type: GrantFiled: August 7, 2020Date of Patent: November 22, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Soojae Park, Younhee Kang, Junghyun Roh
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Patent number: 11315803Abstract: The substrate includes one or more bottom circuit (BC) layers disposed one upon another and one or more front circuit (FC) layers disposed one upon another. The FC layers are disposed on the BC layers. In some embodiments, there are one or more core layers disposed between the FC and BC layers. One or more soft zones are located within and penetrate through one or more of the FC layers. Each soft zone has a soft zone volume which is made of one or more component volumes located in each of one or more of the FC layers. Each soft zone component volume has a soft zone cross sectional area. The soft zone cross sectional areas are located inside a chip boundary projection. The chip boundary projection is a vertical projection of one or more sides of a semiconductor chip through the FC layers. The soft zone volume contains a soft zone material with a Young's modulus that is less than 100 GigaPascals (GPa). Alternative embodiments are presented with outside soft zones outside the chip boundary projection.Type: GrantFiled: May 12, 2020Date of Patent: April 26, 2022Assignee: International Business Machines CorporationInventors: Sri M. Sri-Jayantha, Soojae Park
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Publication number: 20210358769Abstract: The substrate includes one or more bottom circuit (BC) layers disposed one upon another and one or more front circuit (FC) layers disposed one upon another. The FC layers are disposed on the BC layers. In some embodiments, there are one or more core layers disposed between the FC and BC layers. One or more soft zones are located within and penetrate through one or more of the FC layers. Each soft zone has a soft zone volume which is made of one or more component volumes located in each of one or more of the FC layers. Each soft zone component volume has a soft zone cross sectional area. The soft zone cross sectional areas are located inside a chip boundary projection. The chip boundary projection is a vertical projection of one or more sides of a semiconductor chip through the FC layers. The soft zone volume contains a soft zone material with a Young's modulus that is less than 100 GigaPascals (GPa). Alternative embodiments are presented with outside soft zones outside the chip boundary projection.Type: ApplicationFiled: May 12, 2020Publication date: November 18, 2021Inventors: Sri M. Sri-Jayantha, Soojae Park
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Publication number: 20210043592Abstract: A semiconductor package includes a semiconductor substrate, a conductive pad on the semiconductor substrate, a redistribution line conductor, a coating insulator, and an aluminum oxide layer. The redistribution line conductor is electrically connected to the conductive pad. The coating insulator covers the redistribution line conductor and partially exposes the redistribution line conductor. The aluminum oxide layer is provided below the coating insulator and extends along a top surface of the redistribution line conductor, and the aluminum oxide layer is in contact with the redistribution line conductor.Type: ApplicationFiled: August 7, 2020Publication date: February 11, 2021Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Soojae Park, Younhee Kang, Junghyun Roh
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Patent number: 10777495Abstract: A printed circuit board comprises an epoxy-containing member, a first copper pattern disposed adjacent to the epoxy-containing member, and a first adhesion promoter layer interposed between the epoxy-containing member and the first copper pattern.Type: GrantFiled: September 10, 2018Date of Patent: September 15, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventor: Soojae Park
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Publication number: 20190252306Abstract: A printed circuit board comprises an epoxy-containing member, a first copper pattern disposed adjacent to the epoxy-containing member, and a first adhesion promoter layer interposed between the epoxy-containing member and the first copper pattern.Type: ApplicationFiled: September 10, 2018Publication date: August 15, 2019Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventor: SOOJAE PARK
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Patent number: 10147616Abstract: A package frame includes a plurality of unit regions disposed on one surface of the package frame, a peripheral region surrounding the unit regions on the one surface, and a wrinkled structure disposed on the one surface in the peripheral region. A first surface of the wrinkled structure extends from the one surface and is disposed at a different level than the one surface. Each of the unit regions includes a plurality of conductive pads.Type: GrantFiled: October 26, 2015Date of Patent: December 4, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Soojae Park, Geunwoo Kim, Keunho Jang, Younjo Mun
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Patent number: 10134666Abstract: A package substrate including an insulating layer having a top surface and a bottom surface opposite to the top surface, at least one first copper pattern disposed in the insulating layer and adjacent to the top surface of the insulating layer, at least one second copper pattern disposed on the bottom surface of the insulating layer, and at least one embedded aluminum pad disposed on the at least one first copper pattern, the at least one embedded aluminum pad disposed in the insulating layer such that a top surface of the at least one embedded aluminum pad is exposed by the insulating layer may be provided.Type: GrantFiled: March 20, 2018Date of Patent: November 20, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Soojae Park, Kyujin Lee
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Publication number: 20180211909Abstract: A package substrate including an insulating layer having a top surface and a bottom surface opposite to the top surface, at least one first copper pattern disposed in the insulating layer and adjacent to the top surface of the insulating layer, at least one second copper pattern disposed on the bottom surface of the insulating layer, and at least one embedded aluminum pad disposed on the at least one first copper pattern, the at least one embedded aluminum pad disposed in the insulating layer such that a top surface of the at least one embedded aluminum pad is exposed by the insulating layer may be provided.Type: ApplicationFiled: March 20, 2018Publication date: July 26, 2018Applicant: Samsung Electronics Co., Ltd.Inventors: Soojae PARK, Kyujin Lee
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Patent number: 9960107Abstract: A package substrate including an insulating layer having a top surface and a bottom surface opposite to the top surface, at least one first copper pattern disposed in the insulating layer and adjacent to the top surface of the insulating layer, at least one second copper pattern disposed on the bottom surface of the insulating layer, and at least one embedded aluminum pad disposed on the at least one first copper pattern, the at least one embedded aluminum pad disposed in the insulating layer such that a top surface of the at least one embedded aluminum pad is exposed by the insulating layer may be provided.Type: GrantFiled: December 20, 2016Date of Patent: May 1, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Soojae Park, Kyujin Lee
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Publication number: 20170194240Abstract: A package substrate including an insulating layer having a top surface and a bottom surface opposite to the top surface, at least one first copper pattern disposed in the insulating layer and adjacent to the top surface of the insulating layer, at least one second copper pattern disposed on the bottom surface of the insulating layer, and at least one embedded aluminum pad disposed on the at least one first copper pattern, the at least one embedded aluminum pad disposed in the insulating layer such that a top surface of the at least one embedded aluminum pad is exposed by the insulating layer may be provided.Type: ApplicationFiled: December 20, 2016Publication date: July 6, 2017Applicant: Samsung Electronics Co., Ltd.Inventors: Soojae PARK, Kyujin LEE
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Publication number: 20160329275Abstract: The present inventive concept provides a package substrate. The package substrate comprises an insulating substrate having a top surface a circuit pattern disposed on the top surface, and a multilayer conductive joint unit disposed on the circuit pattern. The multilayer conductive joint unit comprises a nickel layer which is in contact with the circuit pattern, and an aluminum layer disposed on the nickel layer and connected to a semiconductor chip mounted on the insulating substrate.Type: ApplicationFiled: May 4, 2016Publication date: November 10, 2016Inventors: Soojae PARK, Moon Gi CHO
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Patent number: 9402315Abstract: Provided is a semiconductor package including a wiring substrate having top and bottom surfaces. A first semiconductor chip is disposed on the wiring substrate in a flip-chip manner. The first semiconductor chip has a first surface facing the top surface of the wiring substrate and a second surface opposite to the first surface. First connection members are disposed between the wiring substrate and the first semiconductor chip. The first connection members include first and second contact members each including one or more magnetic materials. The first contact members include portions disposed in the second contact members. The one or more magnetic material of the first contact members have an opposite polar orientation to that of the second contact members.Type: GrantFiled: August 12, 2014Date of Patent: July 26, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyunsuk Chun, Soojae Park, Seungbae Lee, Sangsu Ha
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Patent number: 9397052Abstract: A semiconductor package includes a package substrate, a first semiconductor chip mounted on the package substrate, a second semiconductor chip mounted on the first semiconductor chip to expose at least a portion of the first semiconductor chip, and a stress-relieving structure provided at an edge of the first semiconductor chip and configured to relieve stress applied between the first semiconductor chip and the second semiconductor chip.Type: GrantFiled: May 30, 2014Date of Patent: July 19, 2016Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Soojae Park, Hyunsuk Chun
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Patent number: 9393633Abstract: A method and apparatus for making chip assemblies is disclosed that prevent or reduce the cracking and delamination of ultra low-k dielectrics in the back-end-of-line in Si chips that can occur during the chip assembly process. The method and apparatus apply pressure to the top and bottom surfaces of a substrate during the chip bonding process so that the bending and warping of the assembled modules are reduced. The reduced bending and warping prevent or reduce the cracking and delamination of ultra low-k dielectrics.Type: GrantFiled: September 1, 2009Date of Patent: July 19, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Pascal P Blais, Paul F Fortier, Kang-Wook Lee, Jae-Woong Nah, Soojae Park, Robert L Toutant, Alain A Warren