Abstract: Provided herein may be a memory system and a method of operating the same. The memory system may include a controller configured to generate and output a first command for a program operation in response to a request from a host, and generate and output a second command for a read scan operation when the memory system is powered on after an abnormal power-off is detected; and a semiconductor memory device configured to perform the program operation on a page basis in response to the first command, perform the read scan operation in response to the second command, and perform a single read operation per page using a set read voltage during the read scan operation.

Abstract: There are provided a memory system and a method for operating the same. A memory system includes: a semiconductor memory device for outputting a ready/busy (R/B) signal by performing an internal operation in response to an operation command, and outputting status data by performing a status check operation in response to a status check command; and a controller for outputting the operation command and the status check command to the semiconductor memory device, and determining validity of the status data, based on the R/B signal.

Abstract: Provided herein may be a memory system and a method of operating the same. The memory system may include a controller configured to generate and output a first command for a program operation in response to a request from a host, and generate and output a second command for a read scan operation when the memory system is powered on after an abnormal power-off is detected; and a semiconductor memory device configured to perform the program operation on a page basis in response to the first command, perform the read scan operation in response to the second command, and perform a single read operation per page using a set read voltage during the read scan operation.

Abstract: A semiconductor memory device includes a status storage unit and a status check unit. The status storage unit stores first status data indicating an operation status of the memory cell array. The status check unit generates second status data, based on the first status data and an operation of the memory cell array.

Abstract: There are provided a memory system and a method for operating the same. A memory system includes: a semiconductor memory device for outputting a ready/busy (R/B) signal by performing an internal operation in response to an operation command, and outputting status data by performing a status check operation in response to a status check command; and a controller for outputting the operation command and the status check command to the semiconductor memory device, and determining validity of the status data, based on the R/B signal.

Abstract: A method of operating a semiconductor memory device includes performing a first program operation in order to raise threshold voltages of memory cells, performing a program verification operation for detecting fast program memory cells, each having a threshold voltage risen higher than a first sub-verification voltage from a second sub-verification voltage or lower, by using a target verification voltage and the first sub-verification voltage and the second sub-verification voltage which are sequentially lower than the target verification voltage, and performing a second program operation under a condition that an increment of each of threshold voltages of memory cells, which is lower than the target verification voltage, is greater than an increment of the threshold voltage of each of the fast program memory cells.

Abstract: A method of operating a semiconductor memory device includes performing a first program operation in order to raise threshold voltages of memory cells, performing a program verification operation for detecting fast program memory cells, each having a threshold voltage risen higher than a first sub-verification voltage from a second sub-verification voltage or lower, by using a target verification voltage and the first sub-verification voltage and the second sub-verification voltage which are sequentially lower than the target verification voltage, and performing a second program operation under a condition that an increment of each of threshold voltages of memory cells, which is lower than the target verification voltage, is greater than an increment of the threshold voltage of each of the fast program memory cells.

Abstract: A method of operating a semiconductor memory device includes performing a first program operation in order to raise threshold voltages of memory cells, performing a program verification operation for detecting fast program memory cells, each having a threshold voltage risen higher than a first sub-verification voltage from a second sub-verification voltage or lower, by using a target verification voltage and the first sub-verification voltage and the second sub-verification voltage which are sequentially lower than the target verification voltage, and performing a second program operation under a condition that an increment of each of threshold voltages of memory cells, which is lower than the target verification voltage, is greater than an increment of the threshold voltage of each of the fast program memory cells.

Abstract: A programming method includes setting the voltages of bit lines, performing a program operation, performing a program verify operation by supplying a program verify voltage and determining whether all of the memory cells of the selected page have been programmed with a target threshold voltage or higher, counting the number of passed memory cells corresponding to a number of pass bits, if, a result of the program verify operation, the program operation failed to program all of the memory cells of the selected page to the target threshold voltage or higher, and making a determination that determines whether the number of pass bits is greater than the first number of pass permission bits, and raising a voltage of a bit line coupled to a failed memory cell, if, as a result of the determination, the number of pass bits is greater than the first number of pass permission bits.

Abstract: A programming method includes setting the voltages of bit lines, performing a program operation, performing a program verify operation by supplying a program verify voltage and determining whether all of the memory cells of the selected page have been programmed with a target threshold voltage or higher, counting the number of passed memory cells corresponding to a number of pass bits, if, a result of the program verify operation, the program operation failed to program all of the memory cells of the selected page to the target threshold voltage or higher, and making a determination that determines whether the number of pass bits is greater than the first number of pass permission bits, and raising a voltage of a bit line coupled to a failed memory cell, if, as a result of the determination, the number of pass bits is greater than the first number of pass permission bits.

Abstract: A method of operating a semiconductor memory device includes performing a first program operation in order to raise threshold voltages of memory cells, performing a program verification operation for detecting fast program memory cells, each having a threshold voltage risen higher than a first sub-verification voltage from a second sub-verification voltage or lower, by using a target verification voltage and the first sub-verification voltage and the second sub-verification voltage which are sequentially lower than the target verification voltage, and performing a second program operation under a condition that an increment of each of threshold voltages of memory cells, which is lower than the target verification voltage, is greater than an increment of the threshold voltage of each of the fast program memory cells.