Abstract: An image recognition method includes the steps of: for a deep learning network that carries out object recognition on a random image, carrying out quantization corresponding to the number of a plurality of different bits to generate a plurality of quantization models respectively corresponding to the number of bits; receiving image data as an input for the deep learning network; determining the uncertainty of the input image data; selecting any one of the plurality of quantization models on the basis of the determined uncertainty; and recognizing an object from the image data by using the selected quantization model, and outputting, as the result of the object recognition, a label corresponding to the image data.

Abstract: An apparatus and method for graphics state management. The apparatus for graphics state management includes a state version manager configured to manage changes in graphics state versions by allocating or deallocating a memory for each of graphics states based on a page of a predetermined size, wherein the state version manager allocates or deallocates pages for each of the graphics state versions by using a string of binary values that indicates the respective reference states of each of those pages.

Abstract: Provided is a method of processing a texture. The method includes acquiring texture position information in a texture image corresponding to pixel position information of pixels constituting a frame, acquiring texture classification information (TCI) representing a similarity between respective texture factors of two or more classified regions in the texture image based on the texture position information, determining an amount of texture data requested from a memory according to the TCI, and reading texture data corresponding to the determined amount of texture data based on the texture position information.

Abstract: Provided is a method of processing a texture. The method includes acquiring texture position information in a texture image corresponding to pixel position information of pixels constituting a frame, acquiring texture classification information (TCI) representing a similarity between respective texture factors of two or more classified regions in the texture image based on the texture position information, determining an amount of texture data requested from a memory according to the TCI, and reading texture data corresponding to the determined amount of texture data based on the texture position information.

Abstract: An apparatus and method for graphics state management. The apparatus for graphics state management includes a state version manager configured to manage changes in graphics state versions by allocating or deallocating a memory for each of graphics states based on a page of a predetermined size, wherein the state version manager allocates or deallocates pages for each of the graphics state versions by using a string of binary values that indicates the respective reference states of each of those pages.

Abstract: A processor including a coarse grained array including a plurality of processing elements, a central register file including a first plurality of register files, a shadow central register file including a second plurality of register files, each of the second plurality of register files corresponding to each of the first plurality of register files included in the central register file, and a plurality of shadow register files, each of the plurality of shadow register files corresponding to each of a third plurality of register files included in predetermined processing elements selected from the plurality of processing elements.

Abstract: A median filtering apparatus and method for removing noise and improving an image quality with respect to all types of input images are provided. The median filtering apparatus may receive an input of N pieces of data, may form a data set including the N pieces of data, may calculate a difference array having an N×N size based on the N pieces of data in the data set, may sum component values for each column of the difference array, and may calculate an index of a column having a smallest value among sum values that are obtained by the summing operation and that are greater than or equal to a preset value.

Abstract: A median filtering apparatus and method for removing noise and improving an image quality with respect to all types of input images are provided. The median filtering apparatus may receive an input of N pieces of data, may form a data set including the N pieces of data, may calculate a difference array having an N×N size based on the N pieces of data in the data set, may sum component values for each column of the difference array, and may calculate an index of a column having a smallest value among sum values that are obtained by the summing operation and that are greater than or equal to a preset value.

Abstract: An apparatus and a method for processing an array in a loop in a computer system, including: applying loop unrolling to a multi-dimensional array included in a loop based on a predetermined unrolling factor to generate a plurality of unrolled multi-dimensional arrays; and transforming each of the plurality of unrolled multi-dimensional arrays into a one-dimensional array having an array subscript expression in a form of an affine function with respect to a loop counter variable.

Abstract: A method, medium, and apparatus to effectively handle an interrupt in a reconfigurable array. In the method, the reconfigurable array pauses execution of an operation when an interrupt request occurs, and after storing register values of a register to be used for handling the interrupt request, an interrupt service is performed by select processing units of the reconfigurable array in response to the interrupt request. Upon completion of the interrupt service, the register values are restored, and the reconfigurable array resumes execution of the operation.

Abstract: A processor including a coarse grained array including a plurality of function units and a plurality of register files, wherein a loop to be executed by the coarse grained array is split into a plurality of sub-loops, and when an interrupt request occurs while executing the sub-loop in the coarse grained array, the interrupt request is processed after the executing of the sub-loop is completed.

Abstract: A reconfigurable processor comprising a configuration memory for storing a configuration bit for at least one loop configuration; a valid information memory for storing bit information indicating whether an operation in a loop is a delay operation; and at least one processing unit for determining whether an operation in a next cycle is the delay operation by referring to the bit information transmitted from the valid information memory, and selectively performing a change and an implementation of a configuration according to the configuration bit from the configuration memory based on the determined results.

Abstract: A profiler which provides information to optimize an application specific architecture processor and a program for the processor is provided.

Abstract: A method, medium, and apparatus to effectively handle an interrupt in a reconfigurable array. In the method, the reconfigurable array pauses execution of an operation when an interrupt request occurs, and after storing register values of a register to be used for handling the interrupt request, an interrupt service is performed by select processing units of the reconfigurable array in response to the interrupt request. Upon completion of the interrupt service, the register values are restored, and the reconfigurable array resumes execution of the operation.

Abstract: An apparatus and a method for processing an array in a loop in a computer system, including: applying loop unrolling to a multi-dimensional array included in a loop based on a predetermined unrolling factor to generate a plurality of unrolled multi-dimensional arrays; and transforming each of the plurality of unrolled multi-dimensional arrays into a one-dimensional array having an array subscript expression in a form of an affine function with respect to a loop counter variable.

Abstract: A processor including a coarse grained array including a plurality of function units and a plurality of register files, wherein a loop to be executed by the coarse grained array is split into a plurality of sub-loops, and when an interrupt request occurs while executing the sub-loop in the coarse grained array, the interrupt request is processed after the executing of the sub-loop is completed.

Abstract: A reconfigurable processor comprising a configuration memory for storing a configuration bit for at least one loop configuration; a valid information memory for storing bit information indicating whether an operation in a loop is a delay operation; and at least one processing unit for determining whether an operation in a next cycle is the delay operation by referring to the bit information transmitted from the valid information memory, and selectively performing a change and an implementation of a configuration according to the configuration bit from the configuration memory based on the determined results.