Patents by Inventor Sook-Joo Kim
Sook-Joo Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9972384Abstract: An electronic device comprising a semiconductor memory unit that includes a resistance variable element formed over a substrate, and including stacked therein a bottom electrode, a variable resistance layer and a top electrode, and a barrier layer formed over the resistance variable element, and including an amorphous silicon layer which is doped with at least one kind of impurity.Type: GrantFiled: April 14, 2017Date of Patent: May 15, 2018Assignee: SK hynix Inc.Inventors: Sook-Joo Kim, Jae-Geun Oh, Keum-Bum Lee, Hyung-Suk Lee
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Patent number: 9871192Abstract: An electronic device including a semiconductor memory is provided. The semiconductor memory may include an interlayer dielectric layer having a hole; a conductive pattern filled in the hole; and a variable resistance element coupled with the conductive pattern over the conductive pattern and storing different data according to a resistance change, wherein the conductive pattern includes a carbon-containing conductive layer in a region adjacent to the variable resistance element.Type: GrantFiled: August 24, 2016Date of Patent: January 16, 2018Assignee: SK hynix Inc.Inventors: Hyung-Suk Lee, Young-Ju Lee, Sook-Joo Kim
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Patent number: 9799704Abstract: An electronic device with improved variable resistance characteristics and a method for fabricating the same are provided. In an embodiment of the disclosed technology, a method for forming an electronic device with a semiconductor memory includes forming a crystalized doped layer over a substrate; forming a barrier layer over the doped layer; forming a metal layer over the barrier layer; and reacting the barrier layer with a portion of the metal layer. The electronic device and the method of fabricating the same according to embodiments of the disclosed technology may have improved variable resistance characteristics.Type: GrantFiled: August 15, 2016Date of Patent: October 24, 2017Assignee: SK hynix Inc.Inventors: Sook-Joo Kim, Jae-Geun Oh, Hyung-Suk Lee
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Publication number: 20170221557Abstract: An electronic device comprising a semiconductor memory unit that includes a resistance variable element formed over a substrate, and including stacked therein a bottom electrode, a variable resistance layer and a top electrode, and a barrier layer formed over the resistance variable element, and including an amorphous silicon layer which is doped with at least one kind of impurity.Type: ApplicationFiled: April 14, 2017Publication date: August 3, 2017Inventors: Sook-Joo Kim, Jae-Geun Oh, Keum-Bum Lee, Hyung-Suk Lee
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Publication number: 20170194558Abstract: An electronic device in accordance with an implementation may include a semiconductor memory, and the semiconductor memory may include an interlayer dielectric layer having a hole; a conductive pattern filled in the hole; and a variable resistance element coupled with the conductive pattern over the conductive pattern and storing different data according to a resistance change, wherein the conductive pattern includes a carbon-containing conductive layer in a region adjacent to the variable resistance element.Type: ApplicationFiled: August 24, 2016Publication date: July 6, 2017Inventors: Hyung-Suk Lee, Young-Ju Lee, Sook-Joo Kim
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Patent number: 9627616Abstract: An electronic device comprising a semiconductor memory unit that includes a resistance variable element formed over a substrate, and including stacked therein a bottom electrode, a variable resistance layer and a top electrode, and a barrier layer formed over the resistance variable element, and including an amorphous silicon layer which is doped with at least one kind of impurity.Type: GrantFiled: March 25, 2014Date of Patent: April 18, 2017Assignee: SK hynix Inc.Inventors: Sook-Joo Kim, Jae-Geun Oh, Keum-Bum Lee, Hyung-Suk Lee
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Publication number: 20160358975Abstract: An electronic device with improved variable resistance characteristics and a method for fabricating the same are provided. In an embodiment of the disclosed technology, a method for forming an electronic device with a semiconductor memory includes forming a crystalized doped layer over a substrate; forming a barrier layer over the doped layer; forming a metal layer over the barrier layer; and reacting the barrier layer with a portion of the metal layer. The electronic device and the method of fabricating the same according to embodiments of the disclosed technology may have improved variable resistance characteristics.Type: ApplicationFiled: August 15, 2016Publication date: December 8, 2016Inventors: Sook-Joo Kim, Jae-Geun Oh, Hyung-Suk Lee
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Patent number: 9418838Abstract: An electronic device with improved variable resistance characteristics and a method for fabricating the same are provided. In an embodiment of the disclosed technology, a method for forming an electronic device with a semiconductor memory includes forming a crystalized doped layer over a substrate; forming a barrier layer over the doped layer; forming a metal layer over the barrier layer; and reacting the barrier layer with a portion of the metal layer. The electronic device and the method of fabricating the same according to embodiments of the disclosed technology may have improved variable resistance characteristics.Type: GrantFiled: July 6, 2015Date of Patent: August 16, 2016Assignee: SK hynix Inc.Inventors: Sook-Joo Kim, Jae-Geun Oh, Hyung-Suk Lee
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Patent number: 9406871Abstract: According to one embodiment, a magnetoresistive element is disclosed. The magnetoresistive element includes a reference layer, a tunnel barrier layer, a storage layer. The storage layer includes a first region and a second region provided outside the first region to surround the first region, the second region including element included in the first region and another element being different from the element. The magnetoresistive element further includes a cap layer including a third region and a fourth region provided outside the third region to surround the third region, the fourth region including an element included in the third region and the another element.Type: GrantFiled: July 23, 2015Date of Patent: August 2, 2016Assignees: KABUSHIKI KAISHA TOSHIBA, SK HYNIX INC.Inventors: Masahiko Nakayama, Masatoshi Yoshikawa, Tadashi Kai, Yutaka Hashimoto, Masaru Toko, Hiroaki Yoda, Jae Geun Oh, Keum Bum Lee, Choon Kun Ryu, Hyung Suk Lee, Sook Joo Kim
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Publication number: 20160181522Abstract: An electronic device with improved variable resistance characteristics and a method for fabricating the same are provided. In an embodiment of the disclosed technology, a method for forming an electronic device with a semiconductor memory includes forming a crystalized doped layer over a substrate; forming a barrier layer over the doped layer; forming a metal layer over the barrier layer; and reacting the barrier layer with a portion of the metal layer. The electronic device and the method of fabricating the same according to embodiments of the disclosed technology may have improved variable resistance characteristics.Type: ApplicationFiled: July 6, 2015Publication date: June 23, 2016Inventors: Sook-Joo Kim, Jae-Geun Oh, Hyung-Suk Lee
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Publication number: 20150325785Abstract: According to one embodiment, a magnetoresistive element is disclosed. The magnetoresistive element includes a reference layer, a tunnel barrier layer, a storage layer. The storage layer includes a first region and a second region provided outside the first region to surround the first region, the second region including element included in the first region and another element being different from the element. The magnetoresistive element further includes a cap layer including a third region and a fourth region provided outside the third region to surround the third region, the fourth region including an element included in the third region and the another element.Type: ApplicationFiled: July 23, 2015Publication date: November 12, 2015Inventors: Masahiko NAKAYAMA, Masatoshi YOSHIKAWA, Tadashi KAI, Yutaka HASHIMOTO, Masaru TOKO, Hiroaki YODA, Jae Geun OH, Keum Bum LEE, Choon Kun RYU, Hyung Suk LEE, Sook Joo KIM
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Patent number: 9123879Abstract: According to one embodiment, a magnetoresistive element is disclosed. The magnetoresistive element includes a reference layer, a tunnel barrier layer, a storage layer. The storage layer includes a first region and a second region provided outside the first region to surround the first region, the second region including element included in the first region and another element being different from the element. The magnetoresistive element further includes a cap layer including a third region and a fourth region provided outside the third region to surround the third region, the fourth region including an element included in the third region and the another element.Type: GrantFiled: March 10, 2014Date of Patent: September 1, 2015Inventors: Masahiko Nakayama, Masatoshi Yoshikawa, Tadashi Kai, Yutaka Hashimoto, Masaru Toko, Hiroaki Yoda, Jae Geun Oh, Keum Bum Lee, Choon Kun Ryu, Hyung Suk Lee, Sook Joo Kim
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Publication number: 20150069557Abstract: According to one embodiment, a magnetoresistive element is disclosed. The magnetoresistive element includes a reference layer, a tunnel barrier layer, a storage layer. The storage layer includes a first region and a second region provided outside the first region to surround the first region, the second region including element included in the first region and another element being different from the element. The magnetoresistive element further includes a cap layer including a third region and a fourth region provided outside the third region to surround the third region, the fourth region including an element included in the third region and the another element.Type: ApplicationFiled: March 10, 2014Publication date: March 12, 2015Inventors: Masahiko NAKAYAMA, Masatoshi YOSHIKAWA, Tadashi KAI, Yutaka HASHIMOTO, Masaru TOKO, Hiroaki YODA, Jae Geun OH, Keum Bum LEE, Choon Kun RYU, Hyung Suk LEE, Sook Joo KIM
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Patent number: 8878240Abstract: A variable resistance memory device that includes a first electrode, a second electrode, a variable resistance layer interposed between the first electrode and a second electrode. A metal oxide electrode is interposed between the first electrode and the variable resistance layer, and the metal oxide electrode does not include a nitrogen constituent.Type: GrantFiled: September 14, 2012Date of Patent: November 4, 2014Assignee: SK Hynix Inc.Inventors: Ji-Won Moon, Sung-Hoon Lee, Sook-Joo Kim
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Publication number: 20140287535Abstract: An electronic device comprising a semiconductor memory unit that includes a resistance variable element formed over a substrate, and including stacked therein a bottom electrode, a variable resistance layer and a top electrode, and a barrier layer formed over the resistance variable element, and including an amorphous silicon layer which is doped with at least one kind of impurity.Type: ApplicationFiled: March 25, 2014Publication date: September 25, 2014Applicant: SK HYNIX INC.Inventors: Sook-Joo Kim, Jae-Geun Oh, Keum-Bum Lee, Hyung-Suk Lee
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Patent number: 8760920Abstract: A semiconductor memory device includes a first memory device formed on a semiconductor substrate, including a first storage unit, a source, and a drain, a second memory device, including a second storage unit, and a bit line, wherein the second memory device is connected in series between the bit line and the drain.Type: GrantFiled: December 30, 2010Date of Patent: June 24, 2014Assignee: Hynix Semiconductor Inc.Inventors: Sook Joo Kim, Min Gyu Sung
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Patent number: 8592899Abstract: A semiconductor device including vertical channel transistor and a method for forming the transistor, which can significantly decrease the resistance of a word line is provided. A vertical channel transistor includes a substrate including pillars each of which has a lower portion corresponding to a channel region. A gate insulation layer is formed over the substrate including the pillars. A metal layer having a low resistance is used for forming a surrounding gate electrode to decrease resistance of a word line. A barrier metal layer is formed between a gate insulation layer and a surrounding gate electrode so that deterioration of characteristics of the insulation layer is prevented. A world line is formed connecting gate electrodes formed over the barrier layer to surround the lower portion of each pillar.Type: GrantFiled: August 16, 2010Date of Patent: November 26, 2013Assignee: SK hynix Inc.Inventors: Se-Aug Jang, Hong-Seon Yang, Heung-Jae Cho, Min-Gyu Sung, Tae-Yoon Kim, Sook-Joo Kim
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Publication number: 20130299763Abstract: A variable resistance memory device that includes a first electrode, a second electrode, a variable resistance layer interposed between the first electrode and a second electrode. A metal oxide electrode is interposed between the first electrode and the variable resistance layer, and the metal oxide electrode does not include a nitrogen constituent.Type: ApplicationFiled: September 14, 2012Publication date: November 14, 2013Inventors: Ji-Won MOON, Sung-Hoon LEE, Sook-Joo KIM
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Patent number: 8362457Abstract: A semiconductor device includes a lower electrode, a variable resistance layer disposed over the lower electrode, the variable resistance layer is included a reactive metal layer being interposed between a plurality of oxide resistive layers and an upper electrode disposed over the variable resistance layer.Type: GrantFiled: November 24, 2010Date of Patent: January 29, 2013Assignee: Hynix Semiconductor Inc.Inventors: Sook-Joo Kim, Min-Gyu Sung, Deok-Sin Kil
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Publication number: 20120092935Abstract: A semiconductor memory device includes a first memory device formed on a semiconductor substrate, including a first storage unit, a source, and a drain, a second memory device, including a second storage unit, and a bit line, wherein the second memory device is connected in series between the bit line and the drain.Type: ApplicationFiled: December 30, 2010Publication date: April 19, 2012Applicant: Hynix Semiconductor Inc.Inventors: Sook Joo KIM, Min Gyu Sung