Abstract: A method for forming an integrated circuit involves forming trench isolation regions (208a) and a damascene gate electrode region (214) simultaneous with one another via overlapping process steps. By performing this simultaneous formation of a trench region (208a) and a damascene gate electrode (214) using a common dielectric layer (208), MOS integrated circuits can be formed with reduced processing steps while simultaneously avoiding adverse polysilicon stringers which are present in prior art damacene-formed gate electrode. A single dielectric layer (208) is deposited in order to provide trench fill material for a trench region (208a) while simultaneously providing the material needed for form an opening (210) which is used to define the dimensions and material content of a gate electrode (214).

Abstract: A method for forming shallow trench isolation (STI) (100) begins by forming an oxidizable layer (106) preferably made of polysilicon. An opening is patterned and etched through this layer (106) to define and form the trench isolation region (108). Silicon sidewalls of the trench (108) and the polysilicon layer (106) are then exposed to an oxidizing ambient to form a thermal oxide trench liner (107a) and an erosion-protection polysilicon-oxide layer (107b). A trench fill material (110a) is then deposited and chemically mechanically polished (CMP) utilizing the polysilicon layer (106) as a polish stop. The final polished trench fill plug comprises an ozone TEOS bulk material (110c) and an annular peripheral upper erosion-protection portion formed of the polysilicon-oxide (107d). The annular polysilicon-oxide protection regions (107d) either reduce or entirely eliminate adverse sidewall parasitic erosion which occurs in conventional trench technology when processing active areas (124).