Abstract: The present disclosure relates to a clock generator and a display device including the same. The clock generator includes a first clock generation circuit configured to output a clock, data, and a timing control signal; a first wiring through which the clock is serially transmitted; a second wiring through which the data is serially transmitted; a third wiring through which a pulse of the timing control signal is serially transmitted; a second clock generation circuit connected to the first clock generation circuit through the first wiring, the second wiring, and the third wiring and configured to generate pre-clocks in which phases are sequentially shifted based on the data and the clock; and a clock adjustment circuit configured to receive the pulse of the timing control signal and the pre-clock and output an output clock.

Abstract: A display device includes a display panel including pixels, and data lines and gate lines connected to the pixels, a timing controller configured to output source driving bit information and gate driving bit information through an intra-interface signal, a source driver configured to generate data driving signal based on the source driving bit information and to supply the data driving signal to the data lines, and a gate driver configured to generate a gate driving signal based on the gate driving bit information and to supply the gate driving signal to the gate lines, wherein the intra-interface signal is configured with predetermined data transmission units and includes both the source driving bit information and the gate driving bit information every 1 data transmission unit.

Abstract: A display apparatus includes a display panel driven based on a first gate clock and a second gate clock, a clock supply circuit including a first output terminal for an output of the first gate clock and a second output terminal for an output of the second gate clock, supplying the first output terminal with one of a gate high voltage and a gate low voltage as a first test voltage, and supplying the second output terminal with the other of the gate high voltage and the gate low voltage as a second test voltage, for a first time immediately after a system power is applied thereto, a power generator generating the gate high voltage and the gate low voltage and supplying the gate high voltage and the gate low voltage to the clock supply circuit, and an overcurrent detector receiving a flag signal to recognize overcurrent from the power generator to shut down the power generator, when the first output terminal and the second output terminal are short-circuited with each other at the first time interval.

Abstract: A display device includes a display panel displaying an image, a scan driver configured to apply scan signals to the display panel, and a power supply configured to apply a gate high voltage and a gate low voltage to the scan driver. The scan driver discharges the display panel based on a second gate high voltage lower than the gate high voltage during a discharging operation of the display panel.

Abstract: The present disclosure may provide a display apparatus including a display panel configured to display an image, a shift register configured to supply a scan signal to the display panel, a level shifter configured to output clock signals for driving the shift register, a power supply configured to supply a gate voltage to the level shifter, and a controller configured to sense a node voltage of a circuit generating the gate voltage, detect a short circuit between the clock signals based on a sensed value and an internal reference value, and control the power supply when the short circuit occurs between the clock signals.

Abstract: A display device includes a display panel including pixels, and data lines and gate lines connected to the pixels, a timing controller configured to output source driving bit information and gate driving bit information through an intra-interface signal, a source driver configured to generate data driving signal based on the source driving bit information and to supply the data driving signal to the data lines, and a gate driver configured to generate a gate driving signal based on the gate driving bit information and to supply the gate driving signal to the gate lines, wherein the intra-interface signal is configured with predetermined data transmission units and includes both the source driving bit information and the gate driving bit information every 1 data transmission unit.

Abstract: A display device includes a display panel including pixels, and data lines and gate lines connected to the pixels, a timing controller configured to output source driving bit information and gate driving bit information through an intra-interface signal, a source driver configured to generate data driving signal based on the source driving bit information and to supply the data driving signal to the data lines, and a gate driver configured to generate a gate driving signal based on the gate driving bit information and to supply the gate driving signal to the gate lines, wherein the intra-interface signal is configured with predetermined data transmission units and includes both the source driving bit information and the gate driving bit information every 1 data transmission unit.

Abstract: The present disclosure provides a light emitting display apparatus including a display panel displaying an image, a power supply supplying a driving voltage to the display panel, a data driver supplying a data voltage to the display panel, a timing controller controlling the power supply and the data driver, and a sensing circuit unit receiving a feedback component of the driving voltage as a feedback voltage and selectively sensing an electrically stabilized period in the feedback voltage based on an internal control signal of the power supply.

Abstract: A light emitting display device includes a display panel, a power supply configured to supply a first potential voltage and a second potential voltage to the display panel, and a switch circuit unit configured to sense the first potential voltage applied to the display panel and to feedback the first potential voltage to the power supply, wherein the power supply compensates for the first potential voltage based on the first potential voltage fed back from the switch circuit unit and to output the compensated first potential voltage.

Abstract: A display device includes a display panel displaying an image, a scan driver configured to apply scan signals to the display panel, and a power supply configured to apply a gate high voltage and a gate low voltage to the scan driver. The scan driver discharges the display panel based on a second gate high voltage lower than the gate high voltage during a discharging operation of the display panel.

Abstract: The present disclosure may provide a display apparatus including a display panel configured to display an image, a shift register configured to supply a scan signal to the display panel, a level shifter configured to output clock signals for driving the shift register, a power supply configured to supply a gate voltage to the level shifter, and a controller configured to sense a node voltage of a circuit generating the gate voltage, detect a short circuit between the clock signals based on a sensed value and an internal reference value, and control the power supply when the short circuit occurs between the clock signals.

Abstract: A display device includes a display panel and a level shifter. The display panel displays images. The level shifter includes a signal pad through which a clock signal to drive the display panel is output and a reverse signal pad through which a reverse clock signal different from the clock signal is output, and the reverse signal pad is in an electrically floated state.

Abstract: The present disclosure provides a light emitting display apparatus including a display panel displaying an image, a power supply supplying a driving voltage to the display panel, a data driver supplying a data voltage to the display panel, a timing controller controlling the power supply and the data driver, and a sensing circuit unit receiving a feedback component of the driving voltage as a feedback voltage and selectively sensing an electrically stabilized period in the feedback voltage based on an internal control signal of the power supply.

Abstract: The present disclosure relates to a level shifter and a display device using the same, and the level shifter includes a first transistor configured to increase a voltage of an output signal, a second transistor configured to lower a voltage of the output signal, a first driver configured to vary a gate voltage of the first transistor in response to a first Vgs signal being varied within a transition time of the output signal, and a second driver configured to vary a gate voltage of the second transistor in response to a second Vgs signal being varied within a transition time of the output signal.

Abstract: A display device can include a gate driver configured to drive gate lines of a panel; a data driver configured to drive data lines of the panel; a timing controller configured to control operations of the gate driver and the data driver; and a level shifter integrated circuit (IC) configured to receive a plurality of control signals from the timing controller, and generate and output a plurality gate control signals for controlling driving of the gate driver, in which the plurality of control signals include an on clock and an off clock, and the level shifter IC stores the on clock and the off clock in buffers based on one or more control signals from the timing controller, generates a plurality of scan clocks by logically processing the on clock and the off clock, and outputs the plurality of scan clocks to the gate driver.

Abstract: A light emitting display device includes a display panel, a power supply configured to supply a first potential voltage and a second potential voltage to the display panel, and a switch circuit unit configured to sense the first potential voltage applied to the display panel and to feedback the first potential voltage to the power supply, wherein the power supply compensates for the first potential voltage based on the first potential voltage fed back from the switch circuit unit and to output the compensated first potential voltage.

Abstract: A display device includes a display panel including pixels, and data lines and gate lines connected to the pixels, a timing controller configured to output source driving bit information and gate driving bit information through an intra-interface signal, a source driver configured to generate data driving signal based on the source driving bit information and to supply the data driving signal to the data lines, and a gate driver configured to generate a gate driving signal based on the gate driving bit information and to supply the gate driving signal to the gate lines, wherein the intra-interface signal is configured with predetermined data transmission units and includes both the source driving bit information and the gate driving bit information every 1 data transmission unit.

Abstract: A display device includes a display panel and a level shifter. The display panel displays images. The level shifter includes a signal pad through which a clock signal to drive the display panel is output and a reverse signal pad through which a reverse clock signal different from the clock signal is output, and the reverse signal pad is in an electrically floated state.

Abstract: The present disclosure relates to a level shifter and a display device using the same, and the level shifter includes a first transistor configured to increase a voltage of an output signal, a second transistor configured to lower a voltage of the output signal, a first driver configured to vary a gate voltage of the first transistor in response to a first Vgs signal being varied within a transition time of the output signal, and a second driver configured to vary a gate voltage of the second transistor in response to a second Vgs signal being varied within a transition time of the output signal.

Abstract: A chip on film and a display device including the same selectively outputs gate transmission signals and data outputs to reduce the number of output pads in a data driving IC. The COF includes first to third groups of data input pads, gate input pads, and output pads. A data driving IC includes first to third groups of output buffers, a first switchable output unit configured to selectively supply gate transmission signals and an output of the first group of output buffers to the first group of output pads, and a second switchable output unit configured to selectively supply the gate transmission signals and an output of the third group of output buffers to the third group of output pads. An output of the second group of output buffers is supplied to the second group of output pads between the first and the third groups of output pads.