Patents by Inventor Soon Eng Low

Soon Eng Low has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Apparatuses and methods for outputting signals during self-heat burn-in modes of operation
    Patent number: 7403027
    Abstract: An apparatus and method for selecting and outputting test patterns and internal signals during various SHBI modes of operation. The apparatus may include multiple input/output (I/O) pins, one or more functional blocks, a Self-Heat Burn-In (SHBI) state machine that is coupled to the I/O pins and the one or more functional blocks, and a logic selector circuitry that is coupled to the SHBI state machine and the one or more functional blocks. The SHBI state machine may provide to the I/O pins with first one or more test patterns during a first SHBI mode of operation, and to provide the one or more functional blocks with second one or more test patterns during a second SHBI mode of operation. The logic selector circuitry is configured to select and output the first one or more test patterns to stress the I/O pins during the first SHBI mode of operation, and to select and output internal signals of the one more functional blocks during the second SHBI mode of operation.
    Type: Grant
    Filed: October 30, 2006
    Date of Patent: July 22, 2008
    Assignee: Intel Corporation
    Inventors: Yuen Tat Lee, Soon Eng Low, Naveendran Balasingam
  • APPARATUSES AND METHODS FOR OUTPUTTING SIGNALS DURING SELF-HEAT BURN-IN MODES OF OPERATION
    Publication number: 20080100327
    Abstract: An apparatus and method for selecting and outputting test patterns and internal signals during various SHBI modes of operation. The apparatus may include multiple input/output (I/O) pins, one or more functional blocks, a Self-Heat Burn-In (SHBI) state machine that is coupled to the I/O pins and the one or more functional blocks, and a logic selector circuitry that is coupled to the SHBI state machine and the one or more functional blocks. The SHBI state machine may provide to the I/O pins with first one or more test patterns during a first SHBI mode of operation, and to provide the one or more functional blocks with second one or more test patterns during a second SHBI mode of operation. The logic selector circuitry is configured to select and output the first one or more test patterns to stress the I/O pins during the first SHBI mode of operation, and to select and output internal signals of the one more functional blocks during the second SHBI mode of operation.
    Type: Application
    Filed: October 30, 2006
    Publication date: May 1, 2008
    Inventors: Yuen Tat Lee, Soon Eng Low, Naveendran Balasingam