Patents by Inventor Soon Fatt Yoon

Soon Fatt Yoon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190252567
    Abstract: A photovoltaic diode comprising an emitter layer of doped Group III-V semiconductor material, having a first conductivity type and a first bandgap in at least part of the layer, an intrinsic layer of dilute nitride Group III-V semiconductor material having a composition given by the formula Ga1-zInzNxAsySb1-x-y, where 0<z<0.20, 0.01<x<0.05, and y>0.80 having a second bandgap, a base layer of semiconductor material having a third bandgap and a second conductivity type opposite to the first conductivity type. The emitter, intrinsic and base layers form a diode junction. The first bandgap is greater than the second bandgap.
    Type: Application
    Filed: April 24, 2019
    Publication date: August 15, 2019
    Inventors: Soon Fatt YOON, Kian Hua TAN, Wan Khai LOKE, Satrio WICAKSONO, Nicholas EKINS-DAUKES, Tomos THOMAS, Andrew David JOHNSON
  • Patent number: 9522521
    Abstract: In various embodiments, an apparatus for separating a stacked arrangement including a first layer, a second layer and a release layer between the first layer and the second layer may be provided. The apparatus may include an attachment surface configured to suspend the stacked arrangement by attaching to the first layer. The apparatus may further include an actuating mechanism configured to form a curvature of the first layer by bending the attachment surface. The apparatus may also include a holder to hold an etchant for etching the release layer to separate the first layer from the second layer.
    Type: Grant
    Filed: April 17, 2013
    Date of Patent: December 20, 2016
    Assignee: Nanyang Technological University
    Inventors: Soon Fatt Yoon, Dawei Xu, Chiew Yong Yeo
  • Publication number: 20150083204
    Abstract: A cell arrangement including a plurality of solar sub cells stacked above one another, wherein at least one solar sub cell of the plurality of solar sub cells comprises an alloy of gallium, nitrogen, arsenic and antimony.
    Type: Application
    Filed: February 25, 2013
    Publication date: March 26, 2015
    Inventors: Soon Fatt Yoon, Kian Hua Tan, Wan Khai Loke, Satrio Wicaksono, Daosheng Li
  • Publication number: 20150053352
    Abstract: In various embodiments, an apparatus for separating a stacked arrangement including a first layer, a second layer and a release layer between the first layer and the second layer may be provided. The apparatus may include an attachment surface configured to suspend the stacked arrangement by attaching to the first layer. The apparatus may further include an actuating mechanism configured to form a curvature of the first layer by bending the attachment surface. The apparatus may also include a holder to hold an etchant for etching the release layer to separate the first layer from the second layer.
    Type: Application
    Filed: April 17, 2013
    Publication date: February 26, 2015
    Inventors: Soon Fatt Yoon, Dawei Xu, Chiew Yong Yeo
  • Patent number: 8202788
    Abstract: Disclosed is a method for fabrication of a semiconductor of gallium nitride arsenide antimonide (GaNAsSb) on a substrate wherein the fabrication is performed at a fabrication temperature followed by annealing at an annealing temperature for an annealing time; wherein at least one of: the fabrication temperature, annealing temperature and annealing time, is controlled for controlling defect formation in the semiconductor so as to achieve predetermined performance characteristics of the semiconductor.
    Type: Grant
    Filed: June 26, 2008
    Date of Patent: June 19, 2012
    Assignee: Nanyang Technological University
    Inventors: Soon Fatt Yoon, Kian Hua Tan, Wan Khai Loke, Satrio Wicaksono, Tien Khee Ng
  • Publication number: 20110039400
    Abstract: Disclosed is a method for fabrication of a semiconductor of gallium nitride arsenide antimonide (GaNAsSb) on a substrate wherein the fabrication is performed at a fabrication temperature followed by annealing at an annealing temperature for an annealing time; wherein at least one of: the fabrication temperature, annealing temperature and annealing time, is controlled for controlling defect formation in the semiconductor so as to achieve predetermined performance characteristics of the semiconductor.
    Type: Application
    Filed: June 26, 2008
    Publication date: February 17, 2011
    Applicant: Nanyang Technological University
    Inventors: Soon Fatt Yoon, Kian Hua Tan, Wan Khai Loke, Satrio Wicaksono, Tien Khee Ng