Abstract: A gate driver includes: a pull-up circuit configured to pull up a gate output signal to a high voltage in response to a signal at a first node of the pull-up circuit; a first pull-down circuit configured to pull down the gate output signal to a low voltage in response to a signal at a second node of the first pull-down circuit; a second pull-down circuit configured to pull down the gate output signal to the low voltage in response to a signal at a third node of the second pull-down circuit; a first selection circuit configured to activate the first pull-down circuit and deactivate the second pull-down circuit based on a first selection signal; and a second selection circuit configured to activate the second pull-down circuit and deactivate the first pull-down circuit based on a second selection signal.

Abstract: A pixel includes a first transistor including a first and second gates, a first capacitor connected between a first node and a third node, a second capacitor connected between a fourth node and the third node, a second transistor receiving a first scan signal and connected between a data line and the first node, a third transistor receiving a second scan signal and connected between a reference voltage line and the first node, a fourth transistor receiving a third scan signal and connected between an initialization line and the third node, a fifth transistor receiving an emission signal and connected between a first power line and the second node, a sixth transistor receiving the second scan signal and connected between the fourth node and the second node, and a light emitting element connected between the third node and a second power line.

Abstract: A pixel includes a first transistor including a first and second gates, a first capacitor connected between a first node and a third node, a second capacitor connected between a fourth node and the third node, a second transistor receiving a first scan signal and connected between a data line and the first node, a third transistor receiving a second scan signal and connected between a reference voltage line and the first node, a fourth transistor receiving a third scan signal and connected between an initialization line and the third node, a fifth transistor receiving an emission signal and connected between a first power line and the second node, a sixth transistor receiving the second scan signal and connected between the fourth node and the second node, and a light emitting element connected between the third node and a second power line.

Abstract: A gate driver includes: a pull-up circuit configured to pull up a gate output signal to a high voltage in response to a signal at a first node of the pull-up circuit; a first pull-down circuit configured to pull down the gate output signal to a low voltage in response to a signal at a second node of the first pull-down circuit; a second pull-down circuit configured to pull down the gate output signal to the low voltage in response to a signal at a third node of the second pull-down circuit; a first selection circuit configured to activate the first pull-down circuit and deactivate the second pull-down circuit based on a first selection signal; and a second selection circuit configured to activate the second pull-down circuit and deactivate the first pull-down circuit based on a second selection signal.

Abstract: A gate driver includes: a pull-up circuit configured to pull up a gate output signal to a high voltage in response to a signal at a first node of the pull-up circuit; a first pull-down circuit configured to pull down the gate output signal to a low voltage in response to a signal at a second node of the first pull-down circuit; a second pull-down circuit configured to pull down the gate output signal to the low voltage in response to a signal at a third node of the second pull-down circuit; a first selection circuit configured to activate the first pull-down circuit and deactivate the second pull-down circuit based on a first selection signal; and a second selection circuit configured to activate the second pull-down circuit and deactivate the first pull-down circuit based on a second selection signal.

Abstract: A light emitting display device includes multiple pixels arranged in multiple pixel rows, a first scan signal generator that provides a first scan signal to the pixels in the pixel rows, a second scan signal generator that provides a second scan signal to the pixels in the pixel rows, a third scan signal generator that provides a third scan signal to the pixels in the pixel rows, and a light emission signal generator that provides a light emission signal to the pixels in the pixel rows. Each of the second scan signal generator, the third scan signal generator, and the light emission signal generator provides a same signal to the pixels in two of the pixel rows.

Abstract: A gate driver includes: a pull-up circuit configured to pull up a gate output signal to a high voltage in response to a signal at a first node of the pull-up circuit; a first pull-down circuit configured to pull down the gate output signal to a low voltage in response to a signal at a second node of the first pull-down circuit; a second pull-down circuit configured to pull down the gate output signal to the low voltage in response to a signal at a third node of the second pull-down circuit; a first selection circuit configured to activate the first pull-down circuit and deactivate the second pull-down circuit based on a first selection signal; and a second selection circuit configured to activate the second pull-down circuit and deactivate the first pull-down circuit based on a second selection signal.

Abstract: A pixel of a display apparatus includes a light emitting element, a first transistor, a second transistor, a first capacitor, and a second capacitor. The first transistor applies a driving current to the light emitting element. The second transistor transmits a data voltage. The first capacitor includes a first end electrically connected to a control electrode of the first transistor, and a second end electrically connected to an output electrode of the second transistor. The second capacitor includes a first end electrically connected to the output electrode of the second transistor, and a second end electrically connected to an output electrode of the first transistor.

Abstract: A power converter may include the following elements: an input terminal for receiving an input voltage; an output terminal for providing an output voltage; a reference member for receiving a reference voltage; a first transistor electrically connected between the reference member and the input terminal; a second transistor electrically connected between the input terminal and the output terminal; a diode electrically connected in parallel with the second transistor; and a controller for selecting a first mode if the input voltage is greater than a first reference voltage level and for selecting a second mode if the input voltage has been less than a second reference voltage level for a reference time period. The first transistor and the diode may generate the output voltage in the first mode. The first transistor and the second transistor may generate the output voltage in the second mode.

Abstract: A power controller includes an inductor coupled to an input terminal to which an input voltage is input, a first switch coupled between the inductor and a first power source voltage output terminal, a second switch coupled between the inductor and a ground, a switch controller controlling a voltage output to the first power source voltage output terminal by controlling duties of the first and second switches according to a feedback voltage input to a feedback terminal corresponding to a voltage output to the first power source voltage output terminal, and a diode coupled between the first power source voltage output terminal and the feedback terminal, and preventing a voltage of the first power source voltage output terminal from increasing higher than a breakdown voltage of the first and second switches.

Abstract: A power supply device includes a voltage range selector, a voltage level controller, and a power supply voltage generator. The voltage range selector generates a range selection signal to select a voltage control range. The voltage level controller generates a voltage level control signal based on a driving condition of a display panel. The power supply voltage generator generates a power supply voltage having a voltage level corresponding to the voltage level control signal within the voltage control range, and supplies the power supply voltage to the display panel.

Abstract: A power converter may include the following elements: an input terminal for receiving an input voltage; an output terminal for providing an output voltage; a reference member for receiving a reference voltage; a first transistor electrically connected between the reference member and the input terminal; a second transistor electrically connected between the input terminal and the output terminal; a diode electrically connected in parallel with the second transistor; and a controller for selecting a first mode if the input voltage is greater than a first reference voltage level and for selecting a second mode if the input voltage has been less than a second reference voltage level for a reference time period. The first transistor and the diode may generate the output voltage in the first mode. The first transistor and the second transistor may generate the output voltage in the second mode.

Abstract: A power controller includes an inductor coupled to an input terminal to which an input voltage is input, a first switch coupled between the inductor and a first power source voltage output terminal, a second switch coupled between the inductor and a ground, a switch controller controlling a voltage output to the first power source voltage output terminal by controlling duties of the first and second switches according to a feedback voltage input to a feedback terminal corresponding to a voltage output to the first power source voltage output terminal, and a diode coupled between the first power source voltage output terminal and the feedback terminal, and preventing a voltage of the first power source voltage output terminal from increasing higher than a breakdown voltage of the first and second switches.

Abstract: A power controller includes an inductor coupled to an input terminal to which an input voltage is input, a first switch coupled between the inductor and a first power source voltage output terminal, a second switch coupled between the inductor and a ground, a switch controller controlling a voltage output to the first power source voltage output terminal by controlling duties of the first and second switches according to a feedback voltage input to a feedback terminal corresponding to a voltage output to the first power source voltage output terminal, and a diode coupled between the first power source voltage output terminal and the feedback terminal, and preventing a voltage of the first power source voltage output terminal from increasing higher than a breakdown voltage of the first and second switches.

Abstract: A DC-DC converter includes a first power source generator, the first power source generator including an input port and a first output port, the first power source generator being configured to receive an input power source to the input port, and being configured to generate a first power source, the first power source being output to the first output port, and a selecting unit, the selecting unit being configured to selectively transmit, to the first power source generator, one of: a feedback voltage, the feedback voltage being input from an external feedback wiring line via a feedback terminal, and a voltage of the first output port.

Abstract: Provided are a method of manufacturing a photomask, in which a hardmask film pattern is used as an etch mask for etching a phase-shift layer under the hardmask film pattern, a blankmask, and a photomask using the blankmask. In the method, a resist film for patterning a hardmask film may be formed to a thin thickness, and the phase-shift layer may be etched using the hardmask film pattern having a high etch selectivity with respect to the phase-shift layer. Accordingly, an optical density may be maintained to be 3.0 due to use of a light-shielding film pattern, thereby increasing the resolution and precision of a pattern, reducing a loading effect, and improving critical dimension (CD) features, such as CD uniformity and CD linearity.

Abstract: A power supply device includes a voltage range selector, a voltage level controller, and a power supply voltage generator. The voltage range selector generates a range selection signal to select a voltage control range. The voltage level controller generates a voltage level control signal based on a driving condition of a display panel. The power supply voltage generator generates a power supply voltage having a voltage level corresponding to the voltage level control signal within the voltage control range, and supplies the power supply voltage to the display panel.

Abstract: An organic light emitting display that includes a display panel, a power supply and a coupling member. The display panel includes scan lines, data lines, first power lines and a plurality of pixels. The power supply is positioned at the outside of the display panel, and supplies first power to the display panel through a coupling member. The coupling member includes first and second coupling portions respectively coupled to the power lines, first and second coupling lines transmitting the first power supplied from the power supply to the respective first and second coupling portions, and a feedback line transmitting the voltage of the second coupling portion to the power supply. Accordingly, it is possible to provide an organic light emitting display capable of precisely controlling the voltage of output power and preventing the deterioration of the luminance of a display panel.

Abstract: Provided are a method of manufacturing a photomask, in which a hardmask film pattern is used as an etch mask for etching a phase-shift layer under the hardmask film pattern, a blankmask, and a photomask using the blankmask. In the method, a resist film for patterning a hardmask film may be formed to a thin thickness, and the phase-shift layer may be etched using the hardmask film pattern having a high etch selectivity with respect to the phase-shift layer. Accordingly, an optical density may be maintained to be 3.0 due to use of a light-shielding film pattern, thereby increasing the resolution and precision of a pattern, reducing a loading effect, and improving critical dimension (CD) features, such as CD uniformity and CD linearity.

Abstract: A DC-DC converter includes a first power source generator, the first power source generator including an input port and a first output port, the first power source generator being configured to receive an input power source to the input port, and being configured to generate a first power source, the first power source being output to the first output port, and a selecting unit, the selecting unit being configured to selectively transmit, to the first power source generator, one of: a feedback voltage, the feedback voltage being input from an external feedback wiring line via a feedback terminal, and a voltage of the first output port.