Abstract: An apparatus and a method for video transmission in a video conferencing system in which in order to efficiently transmit the speaker's picture in meetings, conferences, workshops and the like, the text data is separately transmitted by being separated from the speaker's picture.

Abstract: An apparatus and a method for video transmission in a video conferencing system in which in order to efficiently transmit the speaker's picture in meetings, conferences, workshops and the like, the text data is separately transmitted by being separated from the speaker's picture.

Abstract: A method for controlling the data bit rate of a differential pulse code modulation/discrete cosine transform (DPCM/DCT) video encoder, which is adapted to achieve a bit rate control in accordance with a video signal band compression scheme using a differential pulse code modulation (DPCM) and a discrete cosine transform (DCT), thereby obtaining a supreme picture quality while preventing a buffer overflow or underflow phenomenon from occurring in the encoder. The method includes the steps of determining an initial bit allocation amount for every group of pictures (GOP) of an input video, allocating bits for every picture of each GOP, allocating bits for every macroblock of each picture, determining a quantizer step parameter based on the bit allocation amount, and determining a quantizer step size proportional to the determined quantizer step parameter.

Abstract: A very large scale integrated circuit for performing a bit-serial matrix transposition operation, comprising an input shift register module for inputting N multiplied results of two N.times.N matrixes in the unit of k bits and outputting them in the unit of k/N bits in response to a load signal, a bit-serial transposition module for selecting k/N-bit data from the input shift register module in response to a switching control signal, an output multiplexer module for selecting k/N-bit data from the bit-serial transposition module in response to the switching control signal, and an output register module for inputting output data from the output multiplexer module in the unit of k/N bits and outputting N data in the unit of k bits. According to the present invention, when an N.times.N matrix transposition operation is performed, the operation occupancy of transposition cells becomes 100% after an N-input delay occurs. Also, the processing unit of data becomes smaller by using a bit-serial processing algorithm.