Abstract: Systems and methods are provided to supply a voltage (Vcc) to a primary IC in a switch-mode-power-supply following startup. Briefly, an input voltage (VIN) coupled through a boost-inductor to a switch-pin of the IC is sensed by isolating a DC component (VDC_BSW) of the voltage and checking if VIN is greater than a minimum VIN (VIN_MIN) by comparing VDC_BSW to a starting reference voltage (VREF_START) in the IC. If VDC_BSW is greater than VREF_START, a boost-switch in the IC through which the switch-pin is coupled to ground is cycled on and off to alternately store and discharge energy in the boost-inductor, boosting Vcc. Thereafter, VIN is checked against a maximum input voltage by comparing VDC_BSW to a reference voltage (VREF), greater than VREF_START, and if VDC_BSW is greater than VREF, boost is turned off by turning off and ceasing to cycle the boost-switch, protecting the boost-inductor from current runaway.

Abstract: In an example embodiment, a method comprising identifying, by a primary-side controlled Universal Serial Bus Power Delivery (USB-PD) alternating current to direct current (AC-DC) converter, a first pulse, wherein the first pulse is received from a pulse transformer. The method further includes determining that a threshold duration of time is satisfied. In response to determining that the threshold duration of time is satisfied, the method includes identifying a second pulse, wherein the second pulse is received from the pulse transformer. The first pulse and the second pulse are used for control of a high-side field effect transistor (FET) and a low-side FET, where the high-side FET is coupled to an active clamp flyback (ACF) circuit and the low-side FET is coupled to a flyback transformer of the USB-PD AC-DC converter. In response to identifying the second pulse, the method further includes controlling operation of the high-side FET or the low-side FET.

Abstract: A method comprising controlling operation, by a secondary-side controlled Universal Serial Bus Power Delivery (USB-PD) alternating current to direct current (AC-DC) converter, a low-side field-effect transistor (FET). In response to controlling operation of the low-side FET, the method further includes triggering a zero-cross detection circuit. The method further includes measuring a first period of time between controlling operation of the low-side FET and triggering the zero-cross detection circuit. The method further includes measuring a second period of time between controlling operation of a high-side FET and triggering the zero-cross detection circuit. The method further includes adjusting a third period of time based on the first period of time and the second period of time, wherein the third period of time corresponds to a dead time between controlling operation of the high-side FET and the low-side FET.

Abstract: The present invention provides a DC-DC converter, wherein the DC-DC converter includes a controller, a first switch, a second switch, an inductor and a ripple signal generator. The controller is configured to generate an up signal and a down signal according to an output signal and a ripple signal. The first switch is coupled between an input voltage and a first node, and is controlled by the up signal. The second switch is coupled between the first node and a reference voltage, and is controlled by the down signal. The inductor is coupled between the first node and an output node, and is configured to receive a first signal from the first node to generate the output signal at the output node. The ripple signal generator is configured to generate the ripple signal, and reset the ripple signal every cycle to a specific voltage.

Abstract: The present invention provides a DC-DC converter, wherein the DC-DC converter includes a controller, a first switch, a second switch, an inductor and a ripple signal generator. The controller is configured to generate an up signal and a down signal according to an output signal and a ripple signal. The first switch is coupled between an input voltage and a first node, and is controlled by the up signal. The second switch is coupled between the first node and a reference voltage, and is controlled by the down signal. The inductor is coupled between the first node and an output node, and is configured to receive a first signal from the first node to generate the output signal at the output node. The ripple signal generator is configured to generate the ripple signal, and reset the ripple signal every cycle to a specific voltage.

Abstract: A dual supply circuit uses a dual feedback control, single inductor, dual polarity boost architecture with a low side power FET for end of current recirculation sensing. A dual feedback system tracks the output voltage variations and a low side power FET end of current recirculation sensing utilizes the internal current limit sensing system. Logic defining the state of operations allows the regulator to operate in both single and dual mode to cater to wide application ranges. The positive boost regulator can be operated in a buck mode making the output voltage constant with high input supply.

Abstract: A dual supply circuit uses a dual feedback control, single inductor, dual polarity boost architecture with a low side power FET for end of current recirculation sensing. A dual feedback system tracks the output voltage variations and a low side power FET end of current recirculation sensing utilizes the internal current limit sensing system. Logic defining the state of operations allows the regulator to operate in both single and dual mode to cater to wide application ranges. The positive boost regulator can be operated in a buck mode making the output voltage constant with high input supply.