Abstract: A BPSK modulation circuit for a digital communication transmitter comprising a data generator for generating data, a timing circuit for delaying the data produced from the data generator by timing the data in synchronism with a given pulse, a logic circuit for generating a timing pulse whenever the data from the data generator is inverted, a local oscillator for generating a local oscillating frequency, a phase shifter for shifting the local oscillating frequency to have a phase difference of 90.degree., a first double balanced mixer for modulating the delayed signal of the timing circuit in synchronism with the 90.degree. phase-shifted signal of the phase shifter, a second double balanced mixer for modulating the timing pulse of the logic circuit in synchronism with the local oscillating frequency of the local oscillator, and a signal mixer (synthesizing circuit) for synthesizing the output signals of the first and second balanced mixers.