Patents by Inventor Soon Jin Cho

Soon Jin Cho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20110097553
    Abstract: Disclosed is a trench substrate, which includes a first insulating layer having trenches formed therein, a second insulating layer disposed on a lower surface of the first insulating layer and having laser processability inferior to that of the first insulating layer, and a negative pattern formed in the trenches, and in which the second insulating layer having laser processability inferior to that of the first insulating layer functions as a stopper, so that the trenches having the same shape are formed in the first insulating layer, thus enabling the formation of a fine and uniform circuit pattern. A method of fabricating the trench substrate is also provided.
    Type: Application
    Filed: December 4, 2009
    Publication date: April 28, 2011
    Inventors: Jong Kuk Hong, Soon Jin Cho, Sun Uk Hwang
  • Publication number: 20110095421
    Abstract: There is provided a flip chip package including an electronic device, a board including a conductive pad disposed inside a mounting region of the board on which the electronic device is mounted, and a connection pad disposed outside the mounting region, a resin layer formed on the board and including a trench formed by removing a part of the resin layer, and a dam member provided on the trench and preventing the leakage of an underfill between the mounting region and the connection pad. Since the dam member, formed on the processed resin layer, can prevent the leakage of the underfill, a package defect rate can be lowered, and connection reliability can be improved.
    Type: Application
    Filed: October 27, 2010
    Publication date: April 28, 2011
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Ey Yong Kim, Young Hwan Shin, Soon Jin Cho, Jong Yong Kim, Jin Seok Lee
  • Patent number: 7875340
    Abstract: Disclosed herein is a method of manufacturing a heat radiation substrate, including injection-molding mixed powder of carbon nanotubes and metal in a die to fabricate a metal core having through holes; molding the entire metal core including the through holes with an insulating resin to fabricate a metal core substrate; processing the insulating resin provided in the through holes to form connection holes; and forming a circuit pattern on the metal core substrate in which the connection holes are formed.
    Type: Grant
    Filed: December 26, 2007
    Date of Patent: January 25, 2011
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Seung Hyun Cho, Byoung Youl Min, Soon Jin Cho, Jin Won Choi
  • Publication number: 20100271792
    Abstract: An electronic component package and a method of manufacturing the same are disclosed. The method can include: providing a board, on which a multiple number of pads are formed; forming a solder resist layer, in which an opening superimposing over all of the pads is formed, on the board; forming metal posts over the pads, respectively; mounting an electronic component on the board by bonding the electrodes to the metal posts; and forming an underfill resin layer in the opening such that the underfill resin layer is interposed between the electronic component and the board. The solder resist layer may function as a dam that prevents the underfill resin layer from leaking in lateral directions during the subsequent underfill process so that the additional processes, such as dispensing, etc., that were required for forming a separate dam can be omitted, and the process time and costs can be reduced.
    Type: Application
    Filed: November 4, 2009
    Publication date: October 28, 2010
    Inventors: Jin-Won Choi, Soon-Jin Cho, Hueng-Jae Oh, Seung-Wan Kim, Seon-Jae Mun
  • Patent number: 7736952
    Abstract: A wafer packaging method is disclosed. An aspect of the invention is to provide a wafer packaging method comprising; attaching tape onto one side of a carrier, the carrier having a through-hole formed therein; attaching a wafer onto the tape exposed inside the through-hole such that at least one electrode of the wafer is exposed; and performing a packaging process on the carrier such that the wafer is packaged.
    Type: Grant
    Filed: January 25, 2008
    Date of Patent: June 15, 2010
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Soon-Jin Cho, Jin-Won Choi, Seung-Hyun Cho, Chung-Woo Cho, Dong-Gyu Lee, Seok-Hwan Ahn
  • Publication number: 20100096177
    Abstract: Disclosed herein is a coreless substrate having filled via pads and a method of manufacturing the same. Insulating layers are formed on both sides of a build-up layer, and via-pads are embedded in the insulating layers such that the via-pads are flush with the insulating layers. The via pads are not separated from a substrate, and thus reliability of the pads is increased. Flatness of bumps is increased, and thus bonding of flip chips becomes easy.
    Type: Application
    Filed: January 22, 2009
    Publication date: April 22, 2010
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Seok Kyu Lee, Soon OH Jung, Jong Kuk Hong, Soon Jin Cho
  • Publication number: 20090297801
    Abstract: Disclosed herein is a method of manufacturing a heat radiation substrate, including injection-molding mixed powder of carbon nanotubes and metal in a die to fabricate a metal core having through holes; molding the entire metal core including the through holes with an insulating resin to fabricate a metal core substrate; processing the insulating resin provided in the through holes to form connection holes; and forming a circuit pattern on the metal core substrate in which the connection holes are formed.
    Type: Application
    Filed: December 26, 2007
    Publication date: December 3, 2009
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD
    Inventors: Seung Hyun Cho, Byoung Youl Min, Soon Jin Cho, Jin Won Choi
  • Publication number: 20090183909
    Abstract: A coreless substrate having a plurality of function pads, etched from a metal sheet and having a protruded shape; an insulating layer, the insulating layer being formed on one side of the function pads, a circuit corresponding to a pattern being formed on the insulating layer, a via hole being formed on the insulating layer to electrically connect the function pads and the circuit; and a solder resist, being formed on the insulating layer to protect the surface of the insulating layer. The coreless substrate has a signal delivery characteristic that is improved by eliminating the inner via hole.
    Type: Application
    Filed: March 12, 2009
    Publication date: July 23, 2009
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventor: Soon-Jin CHO
  • Publication number: 20090133253
    Abstract: A method of manufacturing a printed circuit board is disclosed. The method may include: sequentially stacking an acid-resistant first cover layer and an alkali-resistant second cover layer over a copper foil, for a copper clad laminate that includes the copper foil stacked over one side of an insulation layer; forming an intaglio groove by removing portions of the second cover layer, the first cover layer, and the copper clad laminate; stacking a seed layer over the intaglio groove and the second cover layer; removing a portion of the seed layer stacked over the second cover layer, by stripping the second cover layer; forming a plating layer, by plating an inside of the intaglio groove; stripping the first cover layer; and removing the copper foil exposed by the stripping of the first cover layer.
    Type: Application
    Filed: June 18, 2008
    Publication date: May 28, 2009
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Dong-Jin Park, Seung-Hyun Jung, Seung-Chul Kim, Soon-Jin Cho
  • Publication number: 20090136656
    Abstract: A method of manufacturing a printed circuit board is disclosed. The method may include: stacking an anti-plating layer over a copper foil, for a copper clad laminate that includes the copper foil stacked over one side of an insulation layer; forming an intaglio groove, by removing a portion of the anti-plating layer and a portion of the copper clad laminate; stacking a seed layer over a surface of the intaglio groove; forming a plating layer, by plating an inside of the intaglio groove; and removing the anti-plating layer and the copper foil.
    Type: Application
    Filed: June 23, 2008
    Publication date: May 28, 2009
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Dong-Jin Park, Seung-Hyun Jung, Seung-Chul Kim, Soon-Jin Cho
  • Patent number: 7517730
    Abstract: The present invention discloses a method for manufacturing a coreless substrate. The method comprises the steps of (a) forming an insulating layer on one side of a metal sheet; (b) forming a via hole on the insulating layer for electrical connection between the metal sheet and the other side; and (c) forming a plurality of protruded function pads by etching the metal sheet. The coreless substrate and manufacturing method thereof in accordance with the present invention have the signal delivery characteristic that is improved by eliminating the inner via hole.
    Type: Grant
    Filed: October 4, 2006
    Date of Patent: April 14, 2009
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventor: Soon-Jin Cho
  • Publication number: 20090087950
    Abstract: A wafer packaging method is disclosed. An aspect of the invention is to provide a wafer packaging method comprising; attaching tape onto one side of a carrier, the carrier having a through-hole formed therein; attaching a wafer onto the tape exposed inside the through-hole such that at least one electrode of the wafer is exposed; and performing a packaging process on the carrier such that the wafer is packaged.
    Type: Application
    Filed: January 25, 2008
    Publication date: April 2, 2009
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Soon-Jin Cho, Jin-Won Choi, Seung-Hyun Cho, Chung-Woo Cho, Dong-Gyu Lee, Seok-Hwan Ahn
  • Publication number: 20090027864
    Abstract: A printed circuit board and a method of manufacturing the printed circuit board are disclosed. A printed circuit board, which includes an insulation layer, a circuit pattern formed on a surface of the insulation layer that includes at least one pad, and a solder resist which covers the circuit pattern, and in which an opening is formed that exposes a portion of a side and a surface of the pad, can ensure a sufficient amount of attachment area for the pads and the solder resist, to strengthen the adhesion of the pads. Also, the adhesion can be increased between the electronic components and the printed circuit board, and heat release characteristics can be improved.
    Type: Application
    Filed: January 14, 2008
    Publication date: January 29, 2009
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Chung-Woo Cho, Jong-Jin Lee, Soon-Jin Cho, Yong-Duk Lee, Ki-Young Yoo, Woo-Young Lee, Chin-Kwan Kim, Jong-Yong Kim, Dong-Ju Jeon
  • Publication number: 20090025581
    Abstract: This invention relates to a mask for screen printing, which includes a mask body composed of a plurality of pattern areas having holes for screen printing and a peripheral area surrounding the outside of the pattern areas; and a protrusion portion formed in the peripheral area of a back surface of the mask body, and to a screen printing method using the same.
    Type: Application
    Filed: December 26, 2007
    Publication date: January 29, 2009
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Soon Jin Cho, Seon Jae Mun, Jin Won Choi
  • Publication number: 20090026169
    Abstract: A printed circuit board manufacturing system and a manufacturing method thereof are disclosed. A method of manufacturing printed circuit board, comprising: providing a substrate that comprises a pad and an insulation layer covering the pad; acquiring an image of the substrate; acquiring location information of the pad by analyzing the image of the substrate; forming a via hole by removing a part of the insulation layer that corresponds the location information of the pad; and forming a via by filling the via hole with a conductive material, provides improved process conformity, even if the substrate has partial or nonlinear deformation, by considering the location information of the pad in the via hole forming. The improved conformity may allow more flexibility to substrate design and more integrity for circuitries on printed circuit board.
    Type: Application
    Filed: January 22, 2008
    Publication date: January 29, 2009
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Chung-Woo Cho, Soon-Jin Cho, Byung-Bae Seo, Ki-Young Yoo, Seok-Hwan Ahn
  • Publication number: 20080225501
    Abstract: A printed circuit board and a manufacturing method thereof are disclosed. The printed circuit board, which includes a first insulation layer, a first via that penetrates the first insulation layer, and a first pad formed on one surface of the first insulation layer, where a whole of or a portion of the first pad is buried in the first via, has a portion of or the whole of the pad buried in the via, so that the contact area between the pad and the via may be increased, and the printed circuit board can be given greater reliability.
    Type: Application
    Filed: March 14, 2008
    Publication date: September 18, 2008
    Inventors: Chung-Woo Cho, Chang-Sup Ryu, Soon-Jin Cho, Seung-Chul Kim
  • Publication number: 20070084630
    Abstract: The present invention discloses a method for manufacturing a coreless substrate. The method comprises the steps of (a) forming an insulating layer on one side of a metal sheet; (b) forming a via hole on the insulating layer for electrical connection between the metal sheet and the other side; and (c) forming a plurality of protruded function pads by etching the metal sheet. The coreless substrate and manufacturing method thereof in accordance with the present invention have the signal delivery characteristic that is improved by eliminating the inner via hole.
    Type: Application
    Filed: October 4, 2006
    Publication date: April 19, 2007
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventor: Soon-Jin Cho
  • Publication number: 20070018335
    Abstract: A flip chip BGA board is disclosed, in which each of the corners of the board is removed to minimize warpage of the board due to heat applied during the manufacturing process. Embodiments of the invention allow the production of thin boards by preventing warpage of the board, and may provide a board high in reliability since the risk of the chip being separated from the board is reduced.
    Type: Application
    Filed: July 11, 2006
    Publication date: January 25, 2007
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Seung-Hyun Cho, Soon-Jin Cho, Jae-Joon Lee, Se-Jong Oh
  • Patent number: 6400021
    Abstract: Disclosed is a wafer level package and a method for fabricating the wafer level package, in which the contact area between the ball land and the solder ball is enlarged, so that the adhesion force between them is highly strengthened. The wafer level package has a semiconductor chip having a lower dielectric layer formed at a bond pad forming surface thereof. The lower dielectric layer includes vias and grooves, and the bond pads are exposed through the vias. A metal pattern interconnecting the bond pads and the grooves with each other is deposited on the lower dielectric layer. An upper dielectric layer is applied on the lower dielectric layer. The upper dielectric layer has a ball land through which the metal pattern deposited on a surface of the grooves is exposed. A solder ball is mounted on the ball land.
    Type: Grant
    Filed: June 27, 2000
    Date of Patent: June 4, 2002
    Assignee: Hyundai Electronics Industries Co., Ltd.
    Inventor: Soon Jin Cho
  • Patent number: 6222259
    Abstract: Disclosed is a stack package and a method of manufacturing the same. The stack package of the present invention comprises a ceramic capsule. A pair of protruding portions are formed at both upper sides of the ceramic capsule. A first semiconductor chip is attached on the upper face of the ceramic capsule and a second semiconductor chip is attached on a lower face of the ceramic capsule. The first and second semiconductor chips are disposed such that their bonding pads are disposed upwardly, more particularly the second semiconductor chip has a size that its bonding pad may be exposed from both sides of the ceramic capsule. It is preferable to attach a heatsink at the lower face of the second semiconductor chip. The first and second semiconductor chips are electrically connected with a metal wire. A midway portion of the metal wire is laid on the protruding portion of the ceramic capsule.
    Type: Grant
    Filed: September 10, 1999
    Date of Patent: April 24, 2001
    Assignee: Hyundai Electronics Industries Co., Ltd.
    Inventors: Sang Wook Park, Soon Jin Cho