Patents by Inventor SoonKwan KWON

SoonKwan KWON has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9620493
    Abstract: A method of manufacturing a three-dimensional (3D) semiconductor includes dividing each of a plurality of wafers into a plurality of multi-dies each including a plurality of dies; checking whether each of the dies has a defect; storing a result of checking whether each of the dies has a defect and information regarding each of the multi-dies; forming virtual combined structures by combining and stacking all the multi-dies in a predetermined number of layers; forming 3D semiconductor groups by calculating yields of the combined structures based on the result of checking whether each of the dies has a defect and the information regarding each of the multi-dies, selecting a combined structure having a highest yield from among the combined structures, and stacking the multi-dies to have the same structure as the selected combined structure; and forming a 3D semiconductor chip by dividing the 3D semiconductor groups in units of dies.
    Type: Grant
    Filed: June 23, 2015
    Date of Patent: April 11, 2017
    Assignee: Research & Business Foundation Sungkyunkwan University
    Inventors: Joonsung Yang, Soonkwan Kwon
  • Publication number: 20150371980
    Abstract: A method of manufacturing a three-dimensional (3D) semiconductor includes dividing each of a plurality of wafers into a plurality of multi-dies each including a plurality of dies; checking whether each of the dies has a defect; storing a result of checking whether each of the dies has a defect and information regarding each of the multi-dies; forming virtual combined structures by combining and stacking all the multi-dies in a predetermined number of layers; forming 3D semiconductor groups by calculating yields of the combined structures based on the result of checking whether each of the dies has a defect and the information regarding each of the multi-dies, selecting a combined structure having a highest yield from among the combined structures, and stacking the multi-dies to have the same structure as the selected combined structure; and forming a 3D semiconductor chip by dividing the 3D semiconductor groups in units of dies.
    Type: Application
    Filed: June 23, 2015
    Publication date: December 24, 2015
    Applicant: RESEARCH & BUSINESS FOUNDATION SUNGKYUNKWAN UNIVERSITY
    Inventors: Joonsung YANG, Soonkwan KWON
  • Patent number: 9076193
    Abstract: Provided is a method of inspecting a substrate. The method includes: receiving an image of a pad area of substrate; determining and registering a start point pixel; tracing pixels having the same gradation as the start point pixel; determining a boundary area; designating a direction code to next point pixel on the basis of a current point pixel; extracting maximum distance pixel coordinates; and detecting a defect of the pad area.
    Type: Grant
    Filed: December 2, 2013
    Date of Patent: July 7, 2015
    Assignee: Samsung Display Co., Ltd.
    Inventor: SoonKwan Kwon
  • Publication number: 20150003720
    Abstract: Provided is a method of inspecting a substrate. The method includes: receiving an image of a pad area of substrate; determining and registering a start point pixel; tracing pixels having the same gradation as the start point pixel; determining a boundary area; designating a direction code to next point pixel on the basis of a current point pixel; extracting maximum distance pixel coordinates; and detecting a defect of the pad area.
    Type: Application
    Filed: December 2, 2013
    Publication date: January 1, 2015
    Applicant: Samsung Display Co., Ltd.
    Inventor: SoonKwan KWON