Abstract: A thin film transistor array substrate comprising a base substrate, a first wire on the base substrate, a first insulating layer on the base substrate to cover the first wire, a semiconductor layer on the first insulating layer, a second insulating layer on the first insulating layer on which the semiconductor layer is formed, and a second wire on the second insulating layer on the second insulating layer is provided, and a portion of the second wire makes contact with the semiconductor layer through the contact hole.

Abstract: A thin film transistor substrate and a method of manufacturing the same are disclosed. The method of manufacturing a thin film transistor substrate includes forming a first conductive pattern group including a gate line, a gate electrode, and a lower gate pad electrode on a substrate, forming a gate insulating layer on the substrate on which the first conductive pattern group is formed, forming an oxide semiconductor pattern overlapping the gate electrode on the gate insulating layer, and forming first and second conductive layers on the substrate on which the oxide semiconductor pattern is formed and patterning the first and second conductive layers to form a second conductive pattern group including a data line, a source electrode, a drain electrode, and a data pad.

Abstract: A conductive ink composition includes about 15% to about 50% by weight of copper nanoparticles, about 40% to about 80% by weight of a non-aqueous solvent mixture, about 0.01% to about 5% by weight of a dispersion agent and about 1% to about 20% by weight of a wetting agent. A conductive pattern may be formed with use of the conductive ink composition and an inkjet printer.

Abstract: Provided is a method of forming metal wiring. The method includes forming a photosensitive film pattern on a substrate, hydrophobicizing at least part of the photosensitive film pattern, coating metal ink on the substrate having the photosensitive film pattern, forming a seed layer, and forming a metal layer. Alternatively, a trench is formed by using the photosensitive film pattern as a mask, and metal aerosol is sprayed to form the seed layer and then the metal layer. In this method, there is no need to form a metal thin film on the photosensitive film pattern when the seed layer is formed. As a result, less metal is wasted, which, in turn, significantly reduces manufacturing costs.

Abstract: A thin film transistor array substrate comprising a base substrate, a first wire on the base substrate, a first insulating layer on the base substrate to cover the first wire, a semiconductor layer on the first insulating layer, a second insulating layer on the first insulating layer on which the semiconductor layer is formed, and a second wire on the second insulating layer on the second insulating layer is provided, and a portion of the second wire makes contact with the semiconductor layer through the contact hole.

Abstract: A conductive ink composition includes about 15% to about 50% by weight of copper nanoparticles, about 40% to about 80% by weight of a non-aqueous solvent mixture, about 0.01% to about 5% by weight of a dispersion agent and about 1% to about 20% by weight of a wetting agent. A conductive pattern may be formed with use of the conductive ink composition and an inkjet printer.

Abstract: A method of manufacturing a metal nanoparticle includes coupling a metal ion to an organic ligand having a weight-average molecular weight of about 10,000 to about 1,500,000. The method further includes reducing the metal ion coupled to the organic ligand to form a metal nanoparticle having a skin layer.

Abstract: A thin film transistor substrate and a method of manufacturing the same are disclosed. The method of manufacturing a thin film transistor substrate includes forming a first conductive pattern group including a gate line, a gate electrode, and a lower gate pad electrode on a substrate, forming a gate insulating layer on the substrate on which the first conductive pattern group is formed, forming an oxide semiconductor pattern overlapping the gate electrode on the gate insulating layer, and forming first and second conductive layers on the substrate on which the oxide semiconductor pattern is formed and patterning the first and second conductive layers to form a second conductive pattern group including a data line, a source electrode, a drain electrode, and a data pad.

Abstract: The present invention provides a manufacturing method of a thin film transistor array panel comprising forming a gate line on a substrate, forming a gate insulating layer and a semiconductor layer on the gate line in sequence, forming a data line having a source electrode and a drain electrode on the gate insulating layer and the semiconductor layer, and forming a pixel electrode connected to the drain electrode. At least one of the formation of the gate line and the formation of the data line includes a step of forming a slurry layer which is a mixture of conductor particles and a solvent, patterning the slurry layer by using a shaping mold with a prescribed pattern, and removing the shaping mold.

Abstract: A thin film transistor array panel includes a pixel electrode formed on a substrate, a gate line formed on the pixel electrode, a gate insulating film formed on the gate line, a semiconductor formed on the gate insulating film, a data line and a drain electrode formed on the gate insulating film, and a passivation layer formed on portions of the data line and the drain electrode. The gate line includes a first film formed on the same layer and with the same material as the pixel electrode and a second film formed on the first film.

Abstract: Disclosed is a method for manufacturing a high speed bipolar transistor having vertically an emitter zone, a base zone and a collector zone comprising steps of: shielding an active region; forming a bird's beak as a spacer by a field oxidation and etching; forming a base terminal; forming an emitter zone; and metallizing. By the method, a minimum spacing is effectively achieved between the base terminal and the emitter zone of the transistor by utilizing a bird's beak as a spacer by which an exact self alignment between the base terminal and the emitter zone is naturally effected.

Abstract: A method of producing a bipolar CMOS device for providing a unipolar CMOS transistor with a polysilicon gate and a self-aligned NPN and VPNP transistor on a same chip, so that a high performance analog and digital BiCMOS device can be realized.