Abstract: Disclosed is a semiconductor test system comprised of a semiconductor integrated circuit including a plurality of scan cells arranged in first and second directions, and a scan control circuit conducting first and second test operations on the scan cells, from among the plurality of scan cells, arranged along the first and second directions, respectively, and detecting a location of a defective scan cell, from among the plurality of scan cells.

Abstract: Provided are a wafer having an indicator for a first die and a method of attaching a die of the wafer. The wafer includes an indicator formed on a back surface at a position corresponding to a position of a first die on a front surface, for indicating the position of the first die. The method of attaching the die of the wafer includes forming an indicator for a first die, comparing positions of the indicator and the first die, and attaching the die of the wafer. In forming the indicator, the indicator is formed on a back surface of the wafer for indicating the position of the first die. In comparing the positions, the position of the first die formed on a front surface of the wafer is compared with the position of the indicator formed on the back surface of the wafer. If a position error between the positions of the first die and the indicator is smaller than a reference value, the attaching of the die of the wafer performed.