Abstract: Disclosed is an electrode assembly, a battery, and a battery pack and a vehicle including the same. In the electrode assembly, a first electrode, a second electrode, and a separator interposed therebetween are wound based on a winding axis to define a core and an outer circumference. The first electrode includes a first active material portion coated with an active material layer and a first uncoated portion not coated with an active material layer along a winding direction. At least a part of the first uncoated portion is defined as an electrode tab by itself. The first uncoated portion includes a first portion adjacent to the core of the electrode assembly, a second portion adjacent to the outer circumference of the electrode assembly, and a third portion interposed between the first portion and the second portion. The first portion or the second portion has a smaller height than the third portion in the winding axis direction.

Abstract: A method of operating a clock frequency detected control-i/o buffer enable circuit in a semiconductor device uses control I/O buffer enable circuitry and/or features of saving power in standby mode. The method may provide low standby power consumption, such as providing low standby power consumption in high-speed synchronous SRAM and RLDRAM devices.

Abstract: Systems, methods and fabrication processes relating to dynamic random access memory (DRAM) devices involving data signals grouped into 10 bits are disclosed. According to one illustrative implementation a DRAM device may comprise a memory core, circuitry that receives a data bus inversion (DBI) bit associated with a data signal as input directly, without transmission through DBI logic associated with an input buffer, circuitry that stores the DBI bit into the memory core, reads the DBI bit from the memory core, and provides the DBI bit as output. In further implementations, DRAM devices herein may store and process the DBI bit on an internal data bus as a regular data bit.

Abstract: Systems and methods are disclosed involving control I/O buffer enable circuitry and/or features of saving power in standby mode. In illustrative implementations, aspects of the present innovations may be directed to providing low standby power consumption, such as providing low standby power consumption in high-speed synchronous SRAM and RLDRAM devices.

Abstract: A drone control apparatus and method are disclosed. The drone control apparatus according to an exemplary embodiment of the present disclosure includes a communication unit that communicates with a drone operation system and a drone over a wireless communication network, a storage unit that stores radio wave environment information of the wireless communication network according to a spatial position, and flight restriction information, and a determination unit that determines a flight path and a flight altitude of the drone based on a radio map, the flight restriction information, and a departure and a destination of the drone received from the drone operation system, and transmits the flight path and the flight altitude to at least one of the drone and the drone operation system via the communication unit.

Abstract: A method of operating a clock frequency detected control I/O buffer enable circuitry and/or features of saving power. In illustrative implementations, the method may be directed to providing low standby power consumption, such as providing low standby power consumption in high-speed synchronous SRAM and RLDRAM devices.

Abstract: An apparatus and method of managing a network for a drone are disclosed. The apparatus for managing a network for a drone according to an exemplary embodiment of the present disclosure includes a receiver configured to receive first quality information of a base station signal from a drone, a measurer configured to measure second quality information of a base station signal received from the base station, and a determiner configured to determine whether the drone operates as a master drone for relaying the network between at least one child drone and the base station of a communication network based on the received first quality information and the measured second quality information.

Abstract: A drone control apparatus and method are disclosed. The drone control apparatus according to an exemplary embodiment of the present disclosure includes a communication unit that communicates with a drone operation system and a drone over a wireless communication network, a storage unit that stores radio wave environment information of the wireless communication network according to a spatial position, and flight restriction information, and a determination unit that determines a flight path and a flight altitude of the drone based on a radio map, the flight restriction information, and a departure and a destination of the drone received from the drone operation system, and transmits the flight path and the flight altitude to at least one of the drone and the drone operation system via the communication unit.

Abstract: Systems, methods and fabrication processes relating to dynamic random access memory (DRAM) devices involving data signals grouped into 10 bits are disclosed. According to one illustrative implementation a DRAM device may comprise a memory core, circuitry that receives a data bus inversion (DBI) bit associated with a data signal as input directly, without transmission through DBI logic associated with an input buffer, circuitry that stores the DBI bit into the memory core, reads the DBI bit from the memory core, and provides the DBI bit as output. In further implementations, DRAM devices herein may store and process the DBI bit on an internal data bus as a regular data bit.

Abstract: Systems, methods and fabrication processes relating to dynamic random access memory (DRAM) devices involving data signals grouped into 10 bits are disclosed. According to one illustrative implementation a DRAM device may comprise a memory core, circuitry that receives a data bus inversion (DBI) bit associated with a data signal as input directly, without transmission through DBI logic associated with an input buffer, circuitry that stores the DBI bit into the memory core, reads the DBI bit from the memory core, and provides the DBI bit as output. In further implementations, DRAM devices herein may store and process the DBI bit on an internal data bus as a regular data bit.

Abstract: Systems and methods are disclosed involving control I/O buffer enable circuitry and/or features of saving power in standby mode. In illustrative implementations, aspects of the present innovations may be directed to providing low standby power consumption, such as providing low standby power consumption in high-speed synchronous SRAM and RLDRAM devices.

Abstract: Implementations herein involve control I/O buffer enable circuitry and/or features of saving power in standby mode. In illustrative embodiments, aspects of the present innovations may be directed to providing low standby power consumption, such as providing low standby power consumption in high-speed synchronous SRAM and RLDRAM devices.

Abstract: Systems, methods and fabrication processes relating to dynamic random access memory (DRAM) devices involving data signals grouped into 10 bits are disclosed. According to one illustrative implementation a DRAM device may comprise a memory core, circuitry that receives a data bus inversion (DBI) bit associated with a data signal as input directly, without transmission through DBI logic associated with an input buffer, circuitry that stores the DBI bit into the memory core, reads the DBI bit from the memory core, and provides the DBI bit as output. In further implementations, DRAM devices herein may store and process the DBI bit on an internal data bus as a regular data bit.

Abstract: A multi-coexistence communication technology is provided. A multi-coexistence communication system based on an interference-aware environment and a method for operating the same can remove interference detected using an interference temperature limit from at least one transmission signal and transmit the signal to a main/sub communication terminal during data communication on a wired/wireless communication network formed of a main base station, a sub base station, the main communication terminal, and the sub communication terminal, thereby smoothly providing a high-speed seamless data transmission service based on a multi-coexistence communication environment where a distributed small-scale network requiring a low transmission rate, a medium-scale network for providing various wireless communication services, and a large-scale broadcasting network requiring a high transmission rate and high quality coexist, and preventing congestion due to increased demand for frequency resources.

Abstract: A semiconductor integrated memory circuit which extends the time that reliable effective data is output by a data output buffer. The circuit includes a switching device operated by a control signal which is determined according to the states of a row address strobe signal and a column address strobe signal. The switching device is conductive when the column address strobe signal is in an active state, and the switching device is nonconductive when the column address strobe signal is in a precharge state, so that effective data is output by the data output buffer until the column address strobe signal becomes active in the next data read cycle.