Abstract: A random signal generator includes a differential noise generation circuit, an amplification circuit and a single-ended amplifier. The differential noise generation circuit includes a pair of input nodes and a pair of output nodes, and is configured to receive noise signals at the pair of input nodes and to generate differential noise signals at the pair of output nodes. The differential noise generation circuit is self-biased such that the pair of input nodes is coupled to the pair of output nodes. The amplification circuit is configured to amplify the differential noise signals output from the differential noise generation circuit to generate amplified differential signals. The single-ended amplifier is configured to generate a random signal based on the amplified differential signals, the random signal having irregular transition time points.

Abstract: A regulated cascode circuit includes a first MOS transistor of a first conductive type, a second MOS transistor of the first conductive type, a third MOS transistor of a second conductive type, a first current source and a second current source. The first MOS transistor is coupled between an output node and a first node. The second MOS transistor having a gate terminal for receiving a bias voltage is coupled between the first node and a second power supply voltage. The third MOS transistor is coupled between the first power supply voltage and a gate terminal of the first MOS transistor. The first current source is coupled between the gate terminal of the first MOS transistor. The second current source is coupled between the first power supply voltage and the output node.

Abstract: A random signal generator includes a differential noise generation circuit, an amplification circuit and a single-ended amplifier. The differential noise generation circuit includes a pair of input nodes and a pair of output nodes, and is configured to receive noise signals at the pair of input nodes and to generate differential noise signals at the pair of output nodes. The differential noise generation circuit is self-biased such that the pair of input nodes is coupled to the pair of output nodes. The amplification circuit is configured to amplify the differential noise signals output from the differential noise generation circuit to generate amplified differential signals. The single-ended amplifier is configured to generate a random signal based on the amplified differential signals, the random signal having irregular transition time points.

Abstract: A random signal generator circuit includes a thermal noise generator circuit and a self-biased inverter having an input coupled to the thermal noise generator circuit and to a feedback resistor coupled to an output of the self-biased inverter, the self-biased inverter configured to produce a sensed noise signal at the output responsive to thermal noise generated by the thermal noise generator circuit. An amplifier circuit is coupled to the output of the self-biased inverter and configured to amplify the sensed noise signal to produce a saturated random signal. The saturate random signal may be sampled, e.g., with a flip-flop, to generate a random binary signal that may be used for random number generation.

Abstract: A regulated cascode circuit includes a first MOS transistor of a first conductive type, a second MOS transistor of the first conductive type, a third MOS transistor of a second conductive type, a first current source and a second current source. The first MOS transistor is coupled between an output node and a first node. The second MOS transistor having a gate terminal for receiving a bias voltage is coupled between the first node and a second power supply voltage. The third MOS transistor is coupled between the first power supply voltage and a gate terminal of the first MOS transistor. The first current source is coupled between the gate terminal of the first MOS transistor. The second current source is coupled between the first power supply voltage and the output node.

Abstract: An output driver includes a pre-driver that generates first and second gate control signals at first and second nodes. The output driver also includes a main driver that generates an output signal from the first and second gate control signals. The pre-driver includes a capacitor and switches that turn on to forms capacitive current paths between the output node and the first and second nodes during transitions of the output signal for maintaining a slew rate of the output signal.

Abstract: The apparatus for controlling a boosted voltage includes a voltage generating circuit and a control circuit. The voltage generating circuit is configured to generate a boosted voltage from an input voltage based on a control current, and the control circuit is configured to generate the control current based on the boosted voltage.

Abstract: The apparatus for controlling a boosted voltage includes a voltage generating circuit and a control circuit. The voltage generating circuit is configured to generate a boosted voltage from an input voltage based on a control current, and the control circuit is configured to generate the control current based on the boosted voltage.

Abstract: An input buffer comprises: a pull-up transistor connected between a power supply voltage and an input pad and having a gate to which a control voltage is applied, and a substrate to which a floating well voltage is applied; a transmission transistor having a gate to which the power supply voltage is applied and a substrate connected to a ground voltage, and transmitting a signal applied to the input pad; a buffer generating an input signal by buffering the signal applied to the transmission transistor; and a control circuit generating a voltage applied to the input pad as the control voltage and the floating well voltage when a high voltage is applied to the input pad, generating the ground voltage as the control voltage and the power supply voltage as the floating well voltage in the case where a voltage less than the high voltage is applied to the input pad.

Abstract: An input and output circuit of a semiconductor device is disclosed having an output buffer including first and second pull-up transistors connected in series between the power supply voltage and the pad, first and second pull-down transistors connected in series between the pad and the ground voltage, a pre-driver for pulling up or down a voltage of the pad when an output enable signal is enabled and for switching off the first and second pull-up transistors and the first and second pull-down transistors when the output enable signal is disabled, and a first circuit for adjusting voltage differences between respective gates and respective sources/drains of the first and second pull-up transistors and the first and second pull-down transistors to be below a predetermined voltage level in response to the first, second and third control signals under power on or power off conditions; and an input buffer including a transmission gate for transmitting an input signal applied to the pad to a first node in response

Abstract: An input buffer comprises: a pull-up transistor connected between a power supply voltage and an input pad and having a gate to which a control voltage is applied, and a substrate to which a floating well voltage is applied; a transmission transistor having a gate to which the power supply voltage is applied and a substrate connected to a ground voltage, and transmitting a signal applied to the input pad; a buffer generating an input signal by buffering the signal applied to the transmission transistor; and a control circuit generating a voltage applied to the input pad as the control voltage and the floating well voltage when a high voltage is applied to the input pad, generating the ground voltage as the control voltage and the power supply voltage as the floating well voltage in the case where a voltage less than the high voltage is applied to the input pad.

Abstract: An input and output circuit of a semiconductor device is disclosed having an output buffer including first and second pull-up transistors connected in series between the power supply voltage and the pad, first and second pull-down transistors connected in series between the pad and the ground voltage, a pre-driver for pulling up or down a voltage of the pad when an output enable signal is enabled and for switching off the first and second pull-up transistors and the first and second pull-down transistors when the output enable signal is disabled, and a first circuit for adjusting voltage differences between respective gates and respective sources/drains of the first and second pull-up transistors and the first and second pull-down transistors to be below a predetermined voltage level in response to the first, second and third control signals under power on or power off conditions; and an input buffer including a transmission gate for transmitting an input signal applied to the pad to a first node in response

Abstract: An output buffer circuit for reducing a variation of the slew rate due to a variation of process, voltage and temperature (PVT) and the load capacitance of an output terminal, and semiconductor device including the same, include a first slew rate control circuit for pulling down the voltage of a pull-up signal in multiple stages in response to a first control signal, and a second slew rate control circuit for pulling up the voltage of a pull-down signal in multiple stages in response to a second control signal. A pull-up driver is provided for pulling up an output terminal in response to the pull-up signal, and a pull-down driver is provided for pulling down the output terminal in response to the pull-down signal. The first and second slew rate control circuits are controlled by bias voltages that are provided by a phase locked loop circuit and compensate for changes in PVT.

Abstract: An output buffer for buffering output data includes a bias voltage generator for generating first and second bias voltages responsive to a reference voltage, an output driver in signal communication with the bias voltage generator for driving an output terminal, a first slew rate controller in signal communication with the output driver for controlling a pull-up slew rate of the output driver in response to the output data and the first bias voltage, a second slew rate controller in signal communication with the output driver for controlling a pull-down slew rate of the output driver in response to the output data and the second bias voltage, and a slew rate compensator in signal communication with the output ends of the first and second slew rate controllers and the output terminal for compensating for slew rate variation in response to a change in the load capacitance of the output terminal.

Abstract: An output buffer circuit for reducing a variation of the slew rate due to a variation of process, voltage and temperature (PVT) and the load capacitance of an output terminal, and semiconductor device including the same, include a first slew rate control circuit for pulling down the voltage of a pull-up signal in multiple stages in response to a first control signal, and a second slew rate control circuit for pulling up the voltage of a pull-down signal in multiple stages in response to a second control signal. A pull-up driver is provided for pulling up an output terminal in response to the pull-up signal, and a pull-down driver is provided for pulling down the output terminal in response to the pull-down signal. The first and second slew rate control circuits are controlled by bias voltages that are provided by a phase locked loop circuit and compensate for changes in PVT.

Abstract: An output buffer for buffering output data includes a bias voltage generator for generating first and second bias voltages responsive to a reference voltage, an output driver in signal communication with the bias voltage generator for driving an output terminal, a first slew rate controller in signal communication with the output driver for controlling a pull-up slew rate of the output driver in response to the output data and the first bias voltage, a second slew rate controller in signal communication with the output driver for controlling a pull-down slew rate of the output driver in response to the output data and the second bias voltage, and a slew rate compensator in signal communication with the output ends of the first and second slew rate controllers and the output terminal for compensating for slew rate variation in response to a change in the load capacitance of the output terminal.