Patents by Inventor Soon Leng Tan

Soon Leng Tan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Interposer and methods of forming and testing an interposer
    Patent number: 9601424
    Abstract: A method of forming and testing an interposer includes forming vias in a semiconductor material of a wafer having a front side and a back side. The method further includes disposing an electrically conductive layer on the front side of the wafer such that the layer is electrically connected to the vias. The method also includes forming electrically conductive pads on the front side of the wafer, wherein each electrically conductive pad is electrically connected to the electrically conductive layer. The method further includes forming electrically conductive bumps on the back side of the wafer, wherein each electrically conductive bump is electrically connected to at least one via. The method also includes testing electrical connectivity from a first bump to a second bump of the electrically conductive bumps.
    Type: Grant
    Filed: April 13, 2015
    Date of Patent: March 21, 2017
    Assignee: GLOBALFOUNDRIES, INC.
    Inventors: Rahul Agarwal, Jens Oswald, Sheng Feng Lu, Soon Leng Tan, Jeffrey Lam
  • INTERPOSER AND METHODS OF FORMING AND TESTING AN INTERPOSER
    Publication number: 20160300788
    Abstract: A method of forming and testing an interposer includes forming vias in a semiconductor material of a wafer having a front side and a back side. The method further includes disposing an electrically conductive layer on the front side of the wafer such that the layer is electrically connected to the vias. The method also includes forming electrically conductive pads on the front side of the wafer, wherein each electrically conductive pad is electrically connected to the electrically conductive layer. The method further includes forming electrically conductive bumps on the back side of the wafer, wherein each electrically conductive bump is electrically connected to at least one via. The method also includes testing electrical connectivity from a first bump to a second bump of the electrically conductive bumps.
    Type: Application
    Filed: April 13, 2015
    Publication date: October 13, 2016
    Inventors: Rahul Agarwal, Jens Oswald, Sheng Feng Lu, Soon Leng Tan, Jeffrey Lam