Patents by Inventor Soon Lim

Soon Lim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12389041
    Abstract: An encoder determines, based on a width and a height of a block, whether or not to disable a prediction mode in which the block is split along a partitioning line defined by a distance and an angle and then prediction is performed; and encodes the block with the prediction mode disabled or not disabled according to a result of the determination on whether or not to disable the prediction mode. Here, the distance is the shortest distance between the center of the block and the partitioning line, and the angle is an angle representing a direction from the center of the block toward the partitioning line in the shortest distance. The encoder determines to disable the prediction mode when (i) a width-to-height ratio is at least 8 or (ii) a height-to-width ratio is at least 8.
    Type: Grant
    Filed: December 1, 2023
    Date of Patent: August 12, 2025
    Assignee: Panasonic intellectual Property Corporation of America
    Inventors: Jing Ya Li, Che Wei Kuo, Chong Soon Lim, Chu Tong Wang, Han Boon Teo, Hai Wei Sun, Kiyofumi Abe, Takahiro Nishi, Tadamasa Toma, Yusuke Kato
  • Publication number: 20250254309
    Abstract: An image decoding method which can improve both image quality and coding efficiency is an image decoding method for decoding a coded stream which includes a plurality of processing units and a header for the processing units, the coded stream being generated by coding a moving picture, the processing units including at least one processing unit layered to be split into a plurality of smaller processing units, the image decoding method including specifying a hierarchical layer having a processing unit in which a parameter necessary for decoding is stored, by parsing hierarchy depth information stored in the header, and decoding the processing unit using the parameter stored in the processing unit located at the specified hierarchical layer.
    Type: Application
    Filed: April 22, 2025
    Publication date: August 7, 2025
    Inventors: Hisao SASAI, Takahiro NISHI, Youji SHIBAHARA, Chong Soon LIM, Viktor WAHADANIAH, Xuan JING, Sue Mon Thet NAING
  • Publication number: 20250254299
    Abstract: An encoder includes circuitry and memory coupled to the circuitry. The circuitry, in operation, generates a first coefficient value by applying a CCALF (cross component adaptive loop filtering) process to a first reconstructed image sample of a luma component, generates a second coefficient value by applying an ALF (adaptive loop filtering) process to a second reconstructed image sample of a chroma component, and clips the second coefficient value. The circuitry generates a third coefficient value by adding the first coefficient value to the clipped second coefficient value, and clips the third coefficient value. The circuitry encodes a third reconstructed image sample of the chroma component using the clipped third coefficient value.
    Type: Application
    Filed: April 24, 2025
    Publication date: August 7, 2025
    Inventors: Hai Wei SUN, Chong Soon LIM, Jing Ya LI, Han Boon TEO, Che-Wei KUO, Chu Tong WANG, Tadamasa TOMA, Takahiro NISHI, Kiyofumi ABE, Yusuke KATO
  • Patent number: 12375733
    Abstract: An encoder includes circuitry and memory coupled to the circuitry. The circuitry, in response to a first reconstructed image sample being located outside a virtual boundary, duplicates a reconstructed sample located inside and adjacent to the virtual boundary to generate the first reconstructed image sample. The circuitry generates a first coefficient value by applying a CCALF (cross component adaptive loop filtering) process to the first reconstructed image sample of a luma component. The circuitry generates a second coefficient value by applying an ALF (adaptive loop filtering) process to a second reconstructed image sample of a chroma component. The circuitry generates a third coefficient value by adding the first coefficient value to the second coefficient value, and encodes a third reconstructed image sample of the chroma component using the third coefficient value.
    Type: Grant
    Filed: April 17, 2024
    Date of Patent: July 29, 2025
    Assignee: Panasonic Intellectual Property Corporation of America
    Inventors: Chu Tong Wang, Chong Soon Lim, Han Boon Teo, Hai Wei Sun, Jing Ya Li, Che-Wei Kuo, Tadamasa Toma, Takahiro Nishi, Kiyofumi Abe, Yusuke Kato
  • Publication number: 20250240420
    Abstract: An encoder partitions into blocks using a set of block partition modes. The set of block partition modes includes a first partition mode for partitioning a first block, and a second block partition mode for partitioning a second block which is one of blocks obtained after the first block is partitioned. When the number of partitions of the first block partition mode is three, the second block is a center block among the blocks obtained after partitioning the first block, and the partition direction of the second block partition mode is same as the partition direction of the first block partition mode, the second block partition mode indicates that the number of partitions is only three. A parameter for identifying the second block partition mode includes a first flag indicating a horizontal or vertical partition direction, and does not include a second flag indicating the number of partitions.
    Type: Application
    Filed: April 8, 2025
    Publication date: July 24, 2025
    Inventors: Tadamasa TOMA, Takahiro NISHI, Kiyofumi ABE, Ryuichi KANOH, Chong Soon LIM, Sughosh Pavan SHASHIDHAR, Ru Ling LIAO, Hai Wei SUN, Han Boon TEO, Jing Ya LI
  • Publication number: 20250240421
    Abstract: An encoder partitions into blocks using a set of block partition modes. The set of block partition modes includes a first partition mode for partitioning a first block, and a second block partition mode for partitioning a second block which is one of blocks obtained after the first block is partitioned. When the number of partitions of the first block partition mode is three, the second block is a center block among the blocks obtained after partitioning the first block, and the partition direction of the second block partition mode is same as the partition direction of the first block partition mode, the second block partition mode indicates that the number of partitions is only three. A parameter for identifying the second block partition mode includes a first flag indicating a horizontal or vertical partition direction, and does not include a second flag indicating the number of partitions.
    Type: Application
    Filed: April 9, 2025
    Publication date: July 24, 2025
    Inventors: Tadamasa TOMA, Takahiro NISHI, Kiyofumi ABE, Ryuichi KANOH, Chong Soon LIM, Sughosh Pavan SHASHIDHAR, Ru Ling LIAO, Hai Wei SUN, Han Boon TEO, Jing Ya LI
  • Publication number: 20250240410
    Abstract: An encoder includes circuitry and memory connected to the circuitry. The circuitry: derives an absolute value of a sum of horizontal gradient values; derives, as a first parameter, the total sum of the absolute values of horizontal gradient values; derives, as a second parameter, the total sum of the absolute values of vertical gradient values; derives a horizontal-related pixel difference value; derives, as a third parameter, the total sum of the absolute values of horizontal-related pixel difference values; derives a vertical-related pixel difference value; derives, as a fourth parameter, the total sum of the absolute values of vertical-related pixel difference values; and generates a prediction image using the first to fourth parameters.
    Type: Application
    Filed: April 10, 2025
    Publication date: July 24, 2025
    Inventors: Jing Ya LI, Ru Ling LIAO, Chong Soon LIM, Han Boon TEO, Hai Wei SUN, Che Wei KUO, Kiyofumi ABE, Takahiro NISHI, Tadamasa TOMA
  • Publication number: 20250234028
    Abstract: An encoder includes circuitry and a memory coupled to the circuitry, wherein the circuitry, in operation, performs a partition process. The partition process includes calculating first values of a set of pixels between a first partition and a second partition in a current block, using a first motion vector for the first partition; calculating second values of the set of pixels, using a second motion vector for the second partition; and calculating third values of the set of pixels by weighting the first values and the second values. When a ratio of a width to a height of the current block is larger than 4 or a ratio of the height to the width of the current block is larger than 4, the circuitry disables the partition process.
    Type: Application
    Filed: April 4, 2025
    Publication date: July 17, 2025
    Inventors: Kiyofumi ABE, Takahiro NISHI, Tadamasa TOMA, Ryuichi KANOH, Chong Soon LIM, Ru Ling LIAO, Hai Wei SUN, Sughosh Pavan SHASHIDHAR, Han Boon TEO, Jing Ya LI
  • Publication number: 20250234029
    Abstract: A method of performing motion vector prediction for a current block in a picture is provided which includes: deriving a candidate for a motion vector predictor to code a current motion vector of the current block, from a first motion vector of a first block that is spatially adjacent or temporally adjacent to the current block; adding the derived candidate to a list of candidates; and deriving at least one motion vector predictor based on a selected candidate from the list of candidates, wherein the deriving of the candidate includes determining whether to derive the candidate from the first motion vector, based on a type of a current reference picture and a type of a first reference picture, the current reference picture being referred to from the current block using the current motion vector, the first reference picture being referred to from the first block using the first motion vector.
    Type: Application
    Filed: March 28, 2025
    Publication date: July 17, 2025
    Inventors: Chong Soon LIM, Sue Mon Thet Naing, Takahiro Nishi, Hisao Sasai, Youji Shibahara, Toshiyasu Sugio, Kyoko Tanikawa, Toru Matsunobu, Kengo Terada
  • Publication number: 20250233990
    Abstract: An encoder that encodes a current block in a picture includes circuitry and memory. Using the memory, the circuitry: splits the current block into a first sub block, a second sub block, and a third sub block in a first direction, the second sub block being located between the first sub block and the third sub block; prohibits splitting the second sub block into two partitions in the first direction; and encodes the first sub block, the second sub block, and the third sub block.
    Type: Application
    Filed: March 3, 2025
    Publication date: July 17, 2025
    Inventors: Sughosh Pavan SHASHIDHAR, Hai Wei SUN, Chong Soon LIM, Ru Ling LIAO, Han Boon TEO, Jing Ya LI, Takahiro NISHI, Kiyofumi ABE, Ryuichi KANOH, Tadamasa TOMA
  • Publication number: 20250233991
    Abstract: An encoder partitions into blocks using a set of block partition modes. The set of block partition modes includes a first partition mode for partitioning a first block, and a second block partition mode for partitioning a second block which is one of blocks obtained after the first block is partitioned. When the number of partitions of the first block partition mode is three, the second block is a center block among the blocks obtained after partitioning the first block, and the partition direction of the second block partition mode is same as the partition direction of the first block partition mode, the second block partition mode indicates that the number of partitions is only three. A parameter for identifying the second block partition mode includes a first flag indicating a horizontal or vertical partition direction, and does not include a second flag indicating the number of partitions.
    Type: Application
    Filed: April 7, 2025
    Publication date: July 17, 2025
    Inventors: Tadamasa TOMA, Takahiro NISHI, Kiyofumi ABE, Ryuichi KANOH, Chong Soon LIM, Sughosh Pavan SHASHIDHAR, Ru Ling LIAO, Hai Wei SUN, Han Boon TEO, Jing Ya LI
  • Patent number: 12363287
    Abstract: An image encoder includes: circuitry; and a memory coupled to the circuitry. The circuitry, in operation: calculates first values of a current block using intra prediction, the intra prediction being limited to planar mode, the planar mode using multiple reference pixels for each pixel location of the current block; calculates second values of the current block using inter prediction; calculates third values of the current block by weighting the first values and the second values; and encodes the current block using the third values, and in the calculating of the third values, a first weight is applied to the first values and a second weight is applied to the second values, the second weight being different from the first weight.
    Type: Grant
    Filed: May 7, 2024
    Date of Patent: July 15, 2025
    Assignee: PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICA
    Inventors: Ru Ling Liao, Chong Soon Lim, Jing Ya Li, Han Boon Teo, Hai Wei Sun, Che Wei Kuo, Yusuke Kato, Tadamasa Toma, Kiyofumi Abe, Takahiro Nishi
  • Patent number: 12363286
    Abstract: An image encoder includes: circuitry; and a memory coupled to the circuitry. The circuitry, in operation: calculates first values of a current block using intra prediction, the intra prediction being limited to planar mode, the planar mode using multiple reference pixels for each pixel location of the current block; calculates second values of the current block using inter prediction; calculates third values of the current block by weighting the first values and the second values; and encodes the current block using the third values, and in the calculating of the third values, a first weight is applied to the first values and a second weight is applied to the second values, the second weight being different from the first weight.
    Type: Grant
    Filed: May 7, 2024
    Date of Patent: July 15, 2025
    Assignee: PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICA
    Inventors: Ru Ling Liao, Chong Soon Lim, Jing Ya Li, Han Boon Teo, Hai Wei Sun, Che Wei Kuo, Yusuke Kato, Tadamasa Toma, Kiyofumi Abe, Takahiro Nishi
  • Patent number: 12363297
    Abstract: An encoder that encodes a current block in a picture includes circuitry and memory. Using the memory, the circuitry: splits the current block into a first sub block, a second sub block, and a third sub block in a first direction, the second sub block being located between the first sub block and the third sub block; prohibits splitting the second sub block into two partitions in the first direction; and encodes the first sub block, the second sub block, and the third sub block.
    Type: Grant
    Filed: September 6, 2023
    Date of Patent: July 15, 2025
    Assignee: Panasonic Intellectual Property Corporation of America
    Inventors: Sughosh Pavan Shashidhar, Hai Wei Sun, Chong Soon Lim, Ru Ling Liao, Han Boon Teo, Jing Ya Li, Takahiro Nishi, Kiyofumi Abe, Ryuichi Kanoh, Tadamasa Toma
  • Publication number: 20250220233
    Abstract: An encoding device includes memory and a circuit accessible to the memory. In operation, the circuit: encodes first vertex information, second vertex information, and third vertex information into a bitstream, the first vertex information indicating a position of a first vertex of a first triangle, the second vertex information indicating a position of a second vertex of the first triangle, and the third vertex information indicating a position of a third vertex of the first triangle; and encodes angle information into the bitstream, the angle information indicating one or more angles used for identifying a position of a fourth vertex of a second triangle by reference to the first triangle, the second triangle being a triangle that shares a common side with the first triangle and is on the same place as the first triangle.
    Type: Application
    Filed: March 20, 2025
    Publication date: July 3, 2025
    Inventors: Toshiyasu SUGIO, Noritaka IGUCHI, Takahiro NISHI, Chong Soon LIM, Zheng WU, Han Boon TEO, Keng Liang LOI, Chung Dean HAN, Farman DUMANOV
  • Patent number: 12348717
    Abstract: An encoder includes: circuitry; and memory coupled to the circuitry. In the encoder, in operation, the circuitry: performs calculation that involves multiplication and from which a plurality of discrete integers are yieldable as a calculation result, to derive one of the plurality of discrete integers as a quantization parameter threshold; and when orthogonal transform is skipped for a current block of an image, determines a quantization parameter value for the current block, using the quantization parameter threshold. The calculation involves multiplying a first value by a first fixed value, the first value and the first fixed value being each an integer. The first value is a limit value to be included in a header of a bitstream.
    Type: Grant
    Filed: August 16, 2022
    Date of Patent: July 1, 2025
    Assignee: PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICA
    Inventors: Jing Ya Li, Chong Soon Lim, Han Boon Teo, Che Wei Kuo, Hai Wei Sun, Chu Tong Wang, Kiyofumi Abe, Takahiro Nishi, Tadamasa Toma
  • Patent number: 12348725
    Abstract: An image coding method includes: writing, into a sequence parameter set, buffer description defining information for defining a plurality of buffer descriptions; writing, into the sequence parameter set, reference list description defining information for defining a plurality of reference list descriptions corresponding to the buffer descriptions; and writing, into a first header of each processing unit which is included in a coded bitstream, buffer description selecting information for specifying a selected buffer description.
    Type: Grant
    Filed: February 15, 2024
    Date of Patent: July 1, 2025
    Assignee: SUN PATENT TRUST
    Inventors: Viktor Wahadaniah, Chong Soon Lim, Sue Mon Thet Naing, Hai Wei Sun, Takahiro Nishi, Hisao Sasai, Youji Shibahara, Toshiyasu Sugio, Kyoko Tanikawa, Toru Matsunobu, Kengo Terada
  • Publication number: 20250211765
    Abstract: A decoder includes: circuitry; and a memory connected to the circuitry, in which the circuitry, in operation, generates an image by decoding a bitstream, generates a plurality of intermediate feature maps having a uniform size based on the image, generates, based on the plurality of intermediate feature maps, a plurality of feature maps having different sizes for each hierarchical layer in a plurality of hierarchical layers included in a neural network for a machine task, and in generation of the feature maps, for at least one hierarchical layer of the plurality of hierarchical layers, selects any of: a first method of generating the plurality of feature maps of the at least one hierarchical layer using the plurality of intermediate feature maps, and a second method of generating the plurality of feature maps of the at least one hierarchical layer without using the plurality of intermediate feature maps but using the plurality of feature maps generated in a hierarchical layer different from the at least one h
    Type: Application
    Filed: March 10, 2025
    Publication date: June 26, 2025
    Inventors: Jingying GAO, Han Boon TEO, Chong Soon LIM, Praveen Kumar YADAV, Kiyofumi ABE, Takahiro NISHI, Tadamasa TOMA
  • Publication number: 20250203079
    Abstract: An encoder that encodes a current block in a picture includes circuitry and memory. Using the memory, the circuitry: splits the current block into a first sub block, a second sub block, and a third sub block in a first direction, the second sub block being located between the first sub block and the third sub block; prohibits splitting the second sub block into two partitions in the first direction; and encodes the first sub block, the second sub block, and the third sub block.
    Type: Application
    Filed: February 28, 2025
    Publication date: June 19, 2025
    Inventors: Sughosh Pavan SHASHIDHAR, Hai Wei SUN, Chong Soon LIM, Ru Ling LIAO, Han Boon TEO, Jing Ya LI, Takahiro NISHI, Kiyofumi ABE, Ryuichi KANOH, Tadamasa TOMA
  • Publication number: 20250203077
    Abstract: An encoder that encodes a current block in a picture includes circuitry and memory. Using the memory, the circuitry: splits the current block into a first sub block, a second sub block, and a third sub block in a first direction, the second sub block being located between the first sub block and the third sub block; prohibits splitting the second sub block into two partitions in the first direction; and encodes the first sub block, the second sub block, and the third sub block.
    Type: Application
    Filed: February 28, 2025
    Publication date: June 19, 2025
    Inventors: Sughosh Pavan SHASHIDHAR, Hai Wei SUN, Chong Soon LIM, Ru Ling LIAO, Han Boon TEO, Jing Ya LI, Takahiro NISHI, Kiyofumi ABE, Ryuichi KANOH, Tadamasa TOMA