Abstract: In one embodiment, the present invention includes a method for transmitting a frame information structure (FIS) message from a host controller or receiving a FIS message at the host controller, transmitting a synchronization signal from the host controller to a port multiplier coupled to the host controller via a link and sustaining a transmit ready signal from the host controller to the port multiplier to thereby lock the link between the host controller and the port multiplier after sending the synchronization signal, and transmitting multiple command FIS messages from the host controller to the port multiplier in a back-to-back manner, where the back-to-back command FIS messages are directed to different devices. Other embodiments are described and claimed.

Abstract: A method and apparatus for identifying a device associated with a transmission error. The method generally comprising including a device identification information upon detection of a transmission error and further modifying an error check parameter according to a predefined rule.

Abstract: A method, device, system, and computer readable medium are disclosed. In one embodiment the method includes dynamically associating a newly active port in a computer system with a first host controller. The first association happens when a total number of currently active ports in the computer system is less than a maximum capacity number of ports for the first host controller. The method also includes dynamically associating the newly active port in the computer system with a second host controller. The second association happens when the total number of currently active ports in the computer system is greater than or equal to the maximum capacity number of ports for the first host controller. In this method, each port, the first host controller, and second host controller all utilize the same protocol.

Abstract: An apparatus and method for serial link down detection are described. In one embodiment, the method includes the detection of an initial link down condition of a serial link. In one embodiment, the initial link down condition is detected, for example, when a transition from a normal signaling voltage level to a squelch signaling voltage level is detected at a receiver input. When an initial link down condition is detected, the issuance of a link down signal is delayed for a predetermined period of time from the detection of the squelch voltage over the serial link. In one embodiment, the link down signal is asserted if a data error is detected following the predetermined period of time from the detection of the squelch voltage. Other embodiments are described and claimed.

Abstract: A method, device, system, and computer readable medium are disclosed. In one embodiment the method includes dynamically associating a newly active port in a computer system with a first host controller. The first association happens when a total number of currently active ports in the computer system is less than a maximum capacity number of ports for the first host controller. The method also includes dynamically associating the newly active port in the computer system with a second host controller. The second association happens when the total number of currently active ports in the computer system is greater than or equal to the maximum capacity number of ports for the first host controller. In this method, each port, the first host controller, and second host controller all utilize the same protocol.

Abstract: A device shares an existing test signal routing trace with an alternative power supply delivery channel to portions of registers located in combinatorial logic sections.

Abstract: A method and apparatus for identifying a device associated with a transmission error. The method generally comprising including a device identification information upon detection of a transmission error and further modifying an error check parameter according to a predefined rule.

Abstract: In one embodiment, the present invention includes a method for transmitting a frame information structure (FIS) message from a host controller or receiving a FIS message at the host controller, transmitting a synchronization signal from the host controller to a port multiplier coupled to the host controller via a link and sustaining a transmit ready signal from the host controller to the port multiplier to thereby lock the link between the host controller and the port multiplier after sending the synchronization signal, and transmitting multiple command FIS messages from the host controller to the port multiplier in a back-to-back manner, where the back-to-back command FIS messages are directed to different devices. Other embodiments are described and claimed.

Abstract: A device shares an existing test signal routing trace with an alternative power supply delivery channel to portions of registers located in combinatorial logic sections.

Abstract: An apparatus and method for serial link down detection are described. In one embodiment, the method includes the detection of an initial link down condition of a serial link. In one embodiment, the initial link down condition is detected, for example, when a transition from a normal signaling voltage level to a squelch signaling voltage level is detected at a receiver input. When an initial link down condition is detected, the issuance of a link down signal is delayed for a predetermined period of time from the detection of the squelch voltage over the serial link. In one embodiment, the link down signal is asserted if a data error is detected following the predetermined period of time from the detection of the squelch voltage. Other embodiments are described and claimed.