Abstract: A semiconductor device package and methods of manufacturing the same are described. In some examples, a semiconductor device includes an IC die including a ring of die pads around a periphery thereof, lands disposed within the ring of die pads, bond terminals coupled to the lands, the bond terminals being wire-bonded to respective ones of the die pads, and at least one capacitor having respective terminals mounted to respective ones of the lands.

Abstract: A packaged integrated circuit includes an integrated circuit and a package substrate. A trace in the package substrate includes a first portion and a second, high-inductance, portion. The high-inductance portion of the trace is proximate to a port of the integrated circuit and provides a selected inductance operating in cooperation with the capacitance of the port to reduce return loss from the port. The first portion of the trace is part of a transmission line having a characteristic impedance.

Abstract: An IC package includes an IC die mounted on a substrate that includes an ESD protection structure formed within the substrate to dissipate any charge accumulation associated with the package's no-connect pins resulting from human body model ESD and/or voltage spikes during package testing. For some embodiments, the ESD protection structure includes a resistive element formed in the substrate between the no-connect pin and a power plane. For other embodiments, the ESD protection structure includes a conductive ring formed in the substrate and laterally surrounding the land pad of the no-connect pin.

Abstract: A method and apparatus is provided to reduce the spreading inductance and increase the distributed capacitance of power planes within the power distribution system of a semiconductor package substrate. In one embodiment, pre-fabricated copper-clad laminate (CCL) structures are utilized as starting material for the power plane pairs, which are then integrated into a package substrate using imaging, lamination, and drilling/plating processes. In alternate embodiments, a starting material having a larger insulating layer thickness may be used to form the CCL structure, whereby a pair of metallic planes having a perforated mesh pattern are adjoined through a dielectric layer to create an effective separation distance between the metallic planes. Alternate embodiments employ plating or deposition methods to obtain a minimum separation distance between the metallic planes of a power plane pair.

Abstract: A lid having a plurality of recesses at the edges of the lid to provide an improved adhesive bond between the lid and a substrate of an integrated circuit is disclosed. The plurality of recesses may be a castellation comprising a collection of semi-circular cuts into the originally straight edges of the lid. The castellation can be formed by stamping, etching, molding design, or milling/drilling, all of which are well-known methods in the art of forming lids for integrated circuits. The castellation can be vertically straight or it can be slightly tapered, to provide a better locking of the lid on to the package. Epoxy in the recesses can provide an epoxy post for locking the lid. Method of forming a lid having a plurality of recesses and employing a lid on an integrated circuit are also disclosed.

Abstract: A packaged integrated circuit includes an integrated circuit and a package substrate. A trace in the package substrate includes a first portion and a second, high-inductance, portion. The high-inductance portion of the trace is proximate to a port of the integrated circuit and provides a selected inductance operating in cooperation with the capacitance of the port to reduce return loss from the port.

Abstract: A method of producing a carrier wafer for an integrated circuit is disclosed. The method comprises the steps of providing a carrier wafer having a plurality of bump pads and a plurality of wire bond pads; providing a passivation layer on the carrier wafer; etching a passivation layer over at least a portion of the plurality of bump pads; applying solder bumps on the plurality of bump pads; and separately etching the passivation layer over at least a portion of the plurality of wire bond pads. An integrated circuit employing a flip chip is also disclosed.

Abstract: A lid having a plurality of recesses at the edges of the lid to provide an improved adhesive bond between the lid and a substrate of an integrated circuit is disclosed. The plurality of recesses may be a castellation comprising a collection of semi-circular cuts into the originally straight edges of the lid. The castellation can be formed by stamping, etching, molding design, or milling/drilling, all of which are well-known methods in the art of forming lids for integrated circuits. The castellation can be vertically straight or it can be slightly tapered, to provide a better locking of the lid on to the package. Epoxy in the recesses can provide an epoxy post for locking the lid. Method of forming a lid having a plurality of recesses and employing a lid on an integrated circuit are also disclosed.

Abstract: A multi-package module package includes a plurality of individually packaged chips. Yield is increased over conventional multi-chip packages because the individual chips can be inexpensively and fully tested before being placed into the multi-package module package. Also, the manufacturing process is simpler because the individual chips can be more easily handled while being tested and attached to the multi-package module package. Further, a standard component surface mount process is used for package assembly. Thus, no new capital investment or process development is needed.