Patents by Inventor SOON SUK HWANG
SOON SUK HWANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11836041Abstract: A storage device includes a nonvolatile memory device, and a controller that reads first data from the nonvolatile memory device. When a number of first errors of the first data is not smaller than a first threshold value, the controller determines whether the first errors include timing errors arising from a variation of signal transmission timings between the nonvolatile memory device and the controller and performs a retraining operation on the signal transmission timings when the first errors include the timing errors.Type: GrantFiled: August 31, 2022Date of Patent: December 5, 2023Inventors: Chulseung Lee, Soon Suk Hwang, Choongeui Lee
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Publication number: 20230368825Abstract: An operation method of a storage device, which includes a storage controller and a nonvolatile memory device, includes performing first boot-up operation, performing first training on a plurality of data signals such that a detection operation of the first training is repeatedly performed on windows of the data signals, storing offset information generated based on a result of the first training, performing a normal operation based on the result of the first training, performing a second boot-up operation, performing second training on the plurality of data signals based on the offset information generated in the first training such that a detection operation of the second training is repeatedly performed on a left edge section and a right edge section of windows of the data signals, and performing the normal operation based on a result of the second training.Type: ApplicationFiled: July 21, 2023Publication date: November 16, 2023Applicant: Samsung Electronics Co., Ltd.Inventor: Soon Suk HWANG
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Patent number: 11768618Abstract: A data storage device is provided. The data storage device includes: a first function block of a device controller configured to receive user data and perform a first data processing; a first buffer memory connected to the first function block and configured to store user data subjected to the first data processing as first process data; a second function block of the device controller configured to receive a data write command determined based on the first process data; and a non-volatile memory connected to the second function block, and configured to receive and store data stored in the first buffer memory. The user data is provided to the first function block before the data write command is provided to the second function block.Type: GrantFiled: September 7, 2021Date of Patent: September 26, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Young Jin Cho, Hyo Deok Shin, Kyung Bo Yang, Youn Ho Jeon, Hyeok Jun Choe, Jung Hyun Hong, Soon Suk Hwang
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Patent number: 11756599Abstract: An operation method of a storage device, which includes a storage controller and a nonvolatile memory device, includes performing first boot-up operation, performing first training on a plurality of data signals such that a detection operation of the first training is repeatedly performed on windows of the data signals, storing offset information generated based on a result of the first training, performing a normal operation based on the result of the first training, performing a second boot-up operation, performing second training on the plurality of data signals based on the offset information generated in the first training such that a detection operation of the second training is repeatedly performed on a left edge section and a right edge section of windows of the data signals, and performing the normal operation based on a result of the second training.Type: GrantFiled: November 10, 2021Date of Patent: September 12, 2023Assignee: Samsung Electronics Co., Ltd.Inventor: Soon Suk Hwang
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Patent number: 11625063Abstract: A memory system including a memory controller with channel interfaces connecting memory groups via channels. Each channel interface communicates control, address and/or data (CAD) signals to a channel-connected memory group synchronously with a slave clock derived from an input clock. The various slave clocks being uniquely generated by application of channel interface specific phase/frequency modulation or temporal delay, such that the respective CAD signals are characterized by skewed transition timing.Type: GrantFiled: June 3, 2021Date of Patent: April 11, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Young-Jin Cho, Jae-Geun Park, Young-Kwang Yoo, Soon-Suk Hwang
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Publication number: 20220413963Abstract: A storage device includes a nonvolatile memory device, and a controller that reads first data from the nonvolatile memory device. When a number of first errors of the first data is not smaller than a first threshold value, the controller determines whether the first errors include timing errors arising from a variation of signal transmission timings between the nonvolatile memory device and the controller and performs a retraining operation on the signal transmission timings when the first errors include the timing errors.Type: ApplicationFiled: August 31, 2022Publication date: December 29, 2022Inventors: CHULSEUNG LEE, SOON SUK HWANG, CHOONGEUI LEE
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Patent number: 11461172Abstract: A storage device includes a nonvolatile memory device, and a controller that reads first data from the nonvolatile memory device. When a number of first errors of the first data is not smaller than a first threshold value, the controller determines whether the first errors include timing errors arising from a variation of signal transmission timings between the nonvolatile memory device and the controller and performs a retraining operation on the signal transmission timings when the first errors include the timing errors.Type: GrantFiled: March 11, 2021Date of Patent: October 4, 2022Assignee: Samsung Electronics Co., Ltd.Inventors: Chulseung Lee, Soon Suk Hwang, Choongeui Lee
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Publication number: 20220189521Abstract: An operation method of a storage device, which includes a storage controller and a nonvolatile memory device, includes performing first boot-up operation, performing first training on a plurality of data signals such that a detection operation of the first training is repeatedly performed on windows of the data signals, storing offset information generated based on a result of the first training, performing a normal operation based on the result of the first training, performing a second boot-up operation, performing second training on the plurality of data signals based on the offset information generated in the first training such that a detection operation of the second training is repeatedly performed on a left edge section and a right edge section of windows of the data signals, and performing the normal operation based on a result of the second training.Type: ApplicationFiled: November 10, 2021Publication date: June 16, 2022Applicant: Samsung Electronics Co., Ltd.Inventor: Soon Suk HWANG
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Patent number: 11287992Abstract: A storage device includes nonvolatile memory devices arranged in groups, and a controller connected with the groups respectively through channels. The controller is configured to generate an access request for a nonvolatile memory device among the nonvolatile memory devices, and transmit, based on the access request, access requests respectively to two or more groups, among the groups, respectively through two or more channels, among the channels.Type: GrantFiled: February 18, 2020Date of Patent: March 29, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Seonghoon Woo, Soon Suk Hwang
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Publication number: 20210405875Abstract: A data storage device is provided. The data storage device includes: a first function block of a device controller configured to receive user data and perform a first data processing; a first buffer memory connected to the first function block and configured to store user data subjected to the first data processing as first process data; a second function block of the device controller configured to receive a data write command determined based on the first process data; and a non-volatile memory connected to the second function block, and configured to receive and store data stored in the first buffer memory. The user data is provided to the first function block before the data write command is provided to the second function block.Type: ApplicationFiled: September 7, 2021Publication date: December 30, 2021Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Young Jin Cho, Hyo Deok Shin, Kyung Bo Yang, Youn Ho Jeon, Hyeok Jun Choe, Jung Hyun Hong, Soon Suk Hwang
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Patent number: 11137921Abstract: A data storage device is provided. The data storage device includes: a first function block of a device controller configured to receive user data and perform a first data processing; a first buffer memory connected to the first function block and configured to store user data subjected to the first data processing as first process data; a second function block of the device controller configured to receive a data write command determined based on the first process data; and a non-volatile memory connected to the second function block, and configured to receive and store data stored in the first buffer memory. The user data is provided to the first function block before the data write command is provided to the second function block.Type: GrantFiled: September 4, 2019Date of Patent: October 5, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Young Jin Cho, Hyo Deok Shin, Kyung Bo Yang, Youn Ho Jeon, Hyeok Jun Choe, Jung Hyun Hong, Soon Suk Hwang
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Publication number: 20210294376Abstract: A memory system including a memory controller with channel interfaces connecting memory groups via channels. Each channel interface communicates control, address and/or data (CAD) signals to a channel-connected memory group synchronously with a slave clock derived from an input clock. The various slave clocks being uniquely generated by application of channel interface specific phase/frequency modulation or temporal delay, such that the respective CAD signals are characterized by skewed transition timing.Type: ApplicationFiled: June 3, 2021Publication date: September 23, 2021Inventors: YOUNG-JIN CHO, Jae-Geun Park, Young-Kwang Yoo, Soon-Suk Hwang
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Patent number: 11054855Abstract: A memory system including a memory controller with channel interfaces connecting memory groups via channels. Each channel interface communicates control, address and/or data (CAD) signals to a channel-connected memory group synchronously with a slave clock derived from an input clock. The various slave clocks being uniquely generated by application of channel interface specific phase/frequency modulation or temporal delay, such that the respective CAD signals are characterized by skewed transition timing.Type: GrantFiled: October 2, 2018Date of Patent: July 6, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Young-Jin Cho, Jae-Geun Park, Young-Kwang Yoo, Soon-Suk Hwang
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Publication number: 20210200634Abstract: A storage device includes a nonvolatile memory device, and a controller that reads first data from the nonvolatile memory device. When a number of first errors of the first data is not smaller than a first threshold value, the controller determines whether the first errors include timing errors arising from a variation of signal transmission timings between the nonvolatile memory device and the controller and performs a retraining operation on the signal transmission timings when the first errors include the timing errors.Type: ApplicationFiled: March 11, 2021Publication date: July 1, 2021Inventors: CHULSEUNG LEE, SOON SUK HWANG, CHOONGEUI LEE
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Patent number: 10970164Abstract: A storage device includes a nonvolatile memory device, and a controller that reads first data from the nonvolatile memory device. When a number of first errors of the first data is not smaller than a first threshold value, the controller determines whether the first errors include timing errors arising from a variation of signal transmission timings between the nonvolatile memory device and the controller and performs a retraining operation on the signal transmission timings when the first errors include the timing errors.Type: GrantFiled: January 15, 2019Date of Patent: April 6, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Chulseung Lee, Soon Suk Hwang, Choongeui Lee
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Publication number: 20200285392Abstract: A data storage device is provided. The data storage device includes: a first function block of a device controller configured to receive user data and perform a first data processing; a first buffer memory connected to the first function block and configured to store user data subjected to the first data processing as first process data; a second function block of the device controller configured to receive a data write command determined based on the first process data; and a non-volatile memory connected to the second function block, and configured to receive and store data stored in the first buffer memory. The user data is provided to the first function block before the data write command is provided to the second function block.Type: ApplicationFiled: September 4, 2019Publication date: September 10, 2020Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Young Jin CHO, Hyo Deok Shin, Kyung Bo Yang, Youn Ho Jeon, Hyeok Jun Choe, Jung Hyun Hong, Soon Suk Hwang
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Publication number: 20200183600Abstract: A storage device includes nonvolatile memory devices arranged in groups, and a controller connected with the groups respectively through channels. The controller is configured to generate an access request for a nonvolatile memory device among the nonvolatile memory devices, and transmit, based on the access request, access requests respectively to two or more groups, among the groups, respectively through two or more channels, among the channels.Type: ApplicationFiled: February 18, 2020Publication date: June 11, 2020Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Seonghoon WOO, Soon Suk HWANG
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Patent number: 10564876Abstract: A storage device includes nonvolatile memory devices arranged in groups, and a controller connected with the groups respectively through channels. The controller is configured to generate an access request for a nonvolatile memory device among the nonvolatile memory devices, and transmit, based on the access request, access requests respectively to two or more groups, among the groups, respectively through two or more channels, among the channels.Type: GrantFiled: November 6, 2017Date of Patent: February 18, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Seonghoon Woo, Soon Suk Hwang
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Patent number: 10509575Abstract: A storage device includes a nonvolatile memory device, and a controller configured to control the nonvolatile memory device based on metadata. The controller encrypts the metadata and loads the encrypted metadata on a random access memory of an external host device.Type: GrantFiled: January 12, 2017Date of Patent: December 17, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Seonghoon Woo, Haksun Kim, Taemin Jeong, Kyuwook Han, Soon Suk Hwang
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Publication number: 20190354431Abstract: A storage device includes a nonvolatile memory device, and a controller that reads first data from the nonvolatile memory device. When a number of first errors of the first data is not smaller than a first threshold value, the controller determines whether the first errors include timing errors arising from a variation of signal transmission timings between the nonvolatile memory device and the controller and performs a retraining operation on the signal transmission timings when the first errors include the timing errors.Type: ApplicationFiled: January 15, 2019Publication date: November 21, 2019Inventors: CHULSEUNG LEE, SOON SUK HWANG, CHOONGEUI LEE