Abstract: The method for manufacturing an FeRAM capacitor with a merged top electrode plate line (MTP) structure is employed to prevent a detrimental impact on the FeRAM and to secure a reliable FeRAM device. The method includes steps of: preparing an active matrix obtained by a predetermined process; forming a first conductive layer, a dielectric layer and a second conductive layer on the active matrix in sequence; forming a hard mask on the second conductive layer; patterning the second conductive layer, the dielectric layer and the first conductive layer by using the hard mask, thereby forming a vertical capacitor stack, a width of the capacitor stack being larger than that of the storage node contact; forming a second ILD embracing the capacitor stack; planarizing the second ILD till the top face of the hard mask is exposed; removing the hard mask to form an opening above the top electrode; and forming a plate line of which a width is larger than that of the capacitor stack.

Abstract: A semiconductor device and a fabrication method thereof provides a plug structure composed of a diffusion barrier layer formed at the bottom and on the sides of a contact hole and an oxidation barrier layer formed on the diffusion barrier layer that fills up the inside of the contact hole. This invention prevents contact resistance of a bottom electrode and a plug from increasing as well as implementing high-speed operation and improving the reliability of the semiconductor device.

Abstract: The present invention relates to a method for fabricating a ferroelectric random access memory device. The method includes the steps of: (a) forming a first inter-layer insulation layer on a substrate providing a transistor; (b) etching the first inter-layer insulation layer to form a storage node contact hole exposing a partial portion of the substrate; (c) burying a storage node contact including a plug and a barrier metal layer into the storage node contact hole; (d) forming an adhesion layer on the storage node contact and the first inter-layer insulation layer; (e) inducing a predetermined portion of the adhesion layer to be cracked, the predetermined portion disposed above an upper part of the plug; (f) selectively removing the cracked predetermined portion to expose a surface of the barrier metal layer formed on the plug; and (g) forming a ferroelectric capacitor connected to the plug through the exposed surface of the barrier metal layer.

Abstract: The method for manufacturing an FeRAM capacitor with a merged top electrode plate line (MTP) structure is employed to prevent a detrimental impact on the FeRAM and to secure a reliable FeRAM device. The method includes steps of: preparing an active matrix obtained by a predetermined process; forming a first conductive layer, a dielectric layer and a second conductive layer on the active matrix in sequence; forming a hard mask on the second conductive layer; patterning the second conductive layer, the dielectric layer and the first conductive layer by using the hard mask, thereby forming a vertical capacitor stack, a width of the capacitor stack being larger than that of the storage node contact; forming a second ILD embracing the capacitor stack; planarizing the second ILD till the top face of the hard mask is exposed; removing the hard mask to form an opening above the top electrode; and forming a plate line of which a width is larger than that of the capacitor stack.

Abstract: The method for manufacturing an FeRAM capacitor with a merged top electrode plate line (MTP) structure is employed to prevent a detrimental impact on the FeRAM and to secure a reliable FeRAM device. The method includes steps of: preparing an active matrix obtained by a predetermined process; forming a first conductive layer, a dielectric layer and a second conductive layer on the active matrix in sequence; forming a hard mask on the second conductive layer; patterning the second conductive layer, the dielectric layer and the first conductive layer by using the hard mask, thereby forming a vertical capacitor stack, a width of the capacitor stack being larger than that of the storage node contact; forming a second ILD embracing the capacitor stack; planarizing the second ILD till the top face of the hard mask is exposed; removing the hard mask to form an opening above the top electrode; and forming a plate line of which a width is larger than that of the capacitor stack.

Abstract: A method for fabricating a high-density ferroelectric memory device is disclosed in which a plug can be heat-treated at a high temperature. The method includes the following. Forming an interlayer dielectric film on a semiconductor substrate after forming a transistor on the semiconductor substrate. The interlayer dielectric film is selectively etched to form a contact hole. A plug and a barrier film are buried into the contact hole. A conductive film is formed on the interlayer dielectric film including the barrier film. The conductive film is selectively etched to make both ends of the conductive film inclined so as to form a capping layer for capping the barrier film. There are sequentially formed a lower electrode, a ferroelectric thin film and an upper electrode upon the interlayer dielectric film (which includes the capping layer).

Abstract: The present invention provides a ferroelectric memory device capable of suppressing a defect generation due to a charge impact and a method for fabricating the same. The ferroelectric memory device includes: a semiconductor substrate on which a transistor is formed; a semiconductor substrate structure having a transistor; a lower electrode formed on an interfacial insulation layer and connected to a source/drain region of the transistor; an isolating insulation layer on the interfacial insulation layer; a ferroelectric layer covering the isolating insulation layer and lower electrode; an oxygen vacancy compensation layer being formed on the ferroelectric layer and compensating an oxygen vacancy caused by deoxidization of a composition of the ferroelectric layer; and an upper electrode formed on the oxygen vacancy compensation layer.

Abstract: The method for manufacturing an FeRAM capacitor with a merged top electrode plate line (MTP) structure is employed to prevent a detrimental impact on the FeRAM and to secure a reliable FeRAM device. The method includes steps of: preparing an active matrix obtained by a predetermined process; forming a first conductive layer, a dielectric layer and a second conductive layer on the active matrix in sequence; forming a hard mask on the second conductive layer; patterning the second conductive layer, the dielectric layer and the first conductive layer by using the hard mask, thereby forming a vertical capacitor stack, a width of the capacitor stack being larger than that of the storage node contact; forming a second ILD embracing the capacitor stack; planarizing the second ILD till the top face of the hard mask is exposed; removing the hard mask to form an opening above the top electrode; and forming a plate line of which a width is larger than that of the capacitor stack.

Abstract: The present invention relates to a method for fabricating a ferroelectric memory device. The method includes the steps of: forming a first insulation layer on a substrate; forming a storage node contact contacting to a partial portion of the substrate by passing through the first insulation layer; forming a stack pattern of a lower electrode contacting to the storage node contact and a hard mask on the first insulation layer; forming a second insulation layer on an entire surface of the resulting structure including the stack pattern; planarizing the second insulation layer until a surface of the hard mask is exposed; removing selectively the exposed hard mask to make a surface level of the lower electrode lower than that of the second insulation layer; and forming sequentially a ferroelectric layer and an upper electrode on the second insulation layer and the lower electrode.

Abstract: A semiconductor device, capable of precluding the deterioration of flatness and electrical properties due to the non-planarized topology and enhancing oxidative endurance and the process margins, which includes a conductive layer, an insulated layer formed on the conductive layer, a glue layer formed on the insulating layer, a connection unit, which is in contact with the conductive layer through the glue layer and the insulating layer and whose surface is planarized with that of the glue layer and a capacitor including a first electrode formed on the connection unit and the glue layer, a dielectric layer formed on the first electrode and a second electrode formed on the dielectric layer.

Abstract: The present invention provides a ferroelectric memory device capable of suppressing a defect generation due to a charge impact and a method for fabricating the same. The ferroelectric memory device includes: a semiconductor substrate on which a transistor is formed; a semiconductor substrate structure having a transistor; a lower electrode formed on an interfacial insulation layer and connected to a source/drain region of the transistor; an isolating insulation layer on the interfacial insulation layer; a ferroelectric layer covering the isolating insulation layer and lower electrode; an oxygen vacancy compensation layer being formed on the ferroelectric layer and compensating an oxygen vacancy caused by deoxidization of a composition of the ferroelectric layer; and an upper electrode formed on the oxygen vacancy compensation layer.

Abstract: A semiconductor device and a fabrication method thereof provides a plug structure composed of a diffusion barrier layer formed at the bottom and on the sides of a contact hole and an oxidation barrier layer formed on the diffusion barrier layer that fills up the inside of the contact hole. This invention prevents contact resistance of a bottom electrode and a plug from increasing as well as implementing high-speed operation and improving the reliability of the semiconductor device.

Abstract: The present invention relates to a method for fabricating a ferroelectric random access memory device. The method includes the steps of: (a) forming a first inter-layer insulation layer on a substrate providing a transistor; (b) etching the first inter-layer insulation layer to form a storage node contact hole exposing a partial portion of the substrate; (c) burying a storage node contact including a plug and a barrier metal layer into the storage node contact hole; (d) forming an adhesion layer on the storage node contact and the first inter-layer insulation layer; (e) inducing a predetermined portion of the adhesion layer to be cracked, the predetermined portion disposed above an upper part of the plug; (f) selectively removing the cracked predetermined portion to expose a surface of the barrier metal layer formed on the plug; and (g) forming a ferroelectric capacitor connected to the plug through the exposed surface of the barrier metal layer.

Abstract: The present invention provides a ferroelectric memory device capable of suppressing a defect generation due to a charge impact and a method for fabricating the same. The ferroelectric memory device includes: a semiconductor substrate on which a transistor is formed; a semiconductor substrate structure having a transistor; a lower electrode formed on an interfacial insulation layer and connected to a source/drain region of the transistor; an isolating insulation layer on the interfacial insulation layer; a ferroelectric layer covering the isolating insulation layer and lower electrode; an oxygen vacancy compensation layer being formed on the ferroelectric layer and compensating an oxygen vacancy caused by deoxidization of a composition of the ferroelectric layer; and an upper electrode formed on the oxygen vacancy compensation layer.

Abstract: A ferroelectric memory device and a method for manufacturing the same is disclosed. Because a (BixLay)Ti3O12 (BLT) layer, which can be crystallized in relatively low temperature, is used in a capacitor, the electrical characteristics of the ferroelectric capacitor can be improved. The method for manufacturing ferroelectric memory device includes the steps of forming a first conductive layer for a bottom electrode on a semiconductor substrate, forming the (BixLay)Ti3O12 ferroelectric layer, wherein ‘x’ representing atomic concentration of Bi ranges from about 3.25 to about 3.35 and ‘y’ representing atomic concentration of La ranges from about 0.70 to about 0.90 and forming a second conductive layer for a top electrode on the (BixLay)Ti3O12 ferroelectric layer.

Abstract: A semiconductor device and a fabrication method thereof provides a plug structure composed of a diffusion barrier layer formed at the bottom and on the sides of a contact hole and an oxidation barrier layer formed on the diffusion barrier layer that fills up the inside of the contact hole. This invention prevents contact resistance of a bottom electrode and a plug from increasing as well as implementing high-speed operation and improving the reliability of the semiconductor device.

Abstract: Methods for fabricating a ferroelectric memory device are disclosed, in which the cracking of the ferroelectric thin film can be inhibited during a heat treatment in a scribe lane region (for forming an aligning key and an overlay vernier). A first interlayer dielectric film is formed upon a semiconductor substrate on which the transistor has been formed. The first interlayer dielectric film is selectively etched to form a first contact hole and to expose a source/drain. A first conductive film is formed on an entire surface that includes the first contact hole. The first conductive film is selectively etched to form a first conductive pad, the first conductive pad being connected through the first contact hole to the source/drain. A second interlayer dielectric film is formed on an entire surface that includes the first conductive film.

Abstract: The present invention provides a method including the steps of: forming a first diffusion barrier on an insulating layer and in a contact hole; forming a conductive layer on the first diffusion barrier; forming a conductive plug in the contact hole by removing the conductive layer thereby obtaining a first recess in the contact hole, wherein the first recess is surrounded by the conductive layer in the contact hole; etching the first diffusion barrier on the insulating layer thereby forming a second recess in the contact hole, wherein a portion of the conductive plug is surrounded by the second recess and the second recess is surrounded by the insulating layer; removing the portion of the conductive plug surrounded by the second recess thereby forming a third recess in the contact hole, wherein the third recess is surrounded by the insulating layer and bottom of the of the third recess expose the first diffusion barrier and the conductive plug in the contact hole; and forming a second diffusion barrier in the

Abstract: The present invention provides a method including the steps of: forming a first diffusion barrier on an insulating layer and in a contact hole; forming a conductive layer on the first diffusion barrier; forming a conductive plug in the contact hole by removing the conductive layer thereby obtaining a first recess in the contact hole, wherein the first recess is surrounded by the conductive layer in the contact hole; etching the first diffusion barrier on the insulating layer thereby forming a second recess in the contact hole, wherein a portion of the conductive plug is surrounded by the second recess and the second recess is surrounded by the insulating layer; removing the portion of the conductive plug surrounded by the second recess thereby forming a third recess in the contact hole, wherein the third recess is surrounded by the insulating layer and bottom of the of the third recess expose the first diffusion barrier and the conductive plug in the contact hole; and forming a second diffusion barrier in the

Abstract: Provided is a method for forming a semiconductor device that can reduce contact resistance of a storage node contact connecting the source/drain of a transistor with a capacitor. The method includes the steps of: forming an inter-layer insulating layer on a silicon substrate, wherein a junction is formed on a surface of the silicon substrate; forming a contact hole exposing the junction by selectively etching the inter-layer insulating layer; removing a native silicon oxide layer on the junction by forming titanium layer on the junction; and forming a titanium silicide layer as a first ohmic contact layer on the junction by carrying out a first thermal treatment.