Abstract: A photonic crystal laser and a strain measuring device are provided. The photonic crystal laser includes a disk-shaped photonic crystal structure two-dimensionally disposed in a matrix on a disposition plane and a flexible substrate disposed to support the photonic crystal structure and to cover at least a side surface of the photonic crystal structure.

Abstract: A photonic crystal laser and a strain measuring device are provided. The photonic crystal laser includes a disk-shaped photonic crystal structure two-dimensionally disposed in a matrix on a disposition plane and a flexible substrate disposed to support the photonic crystal structure and to cover at least a side surface of the photonic crystal structure.

Abstract: The present disclosure relates to a nanolaser generator using a transparent graphene electrode, a method for manufacturing the same, and a single nanopillar LED using the same. The nanolaser generator includes a microdisk resonator, a protruding dielectric ring provided to surround a boundary surface of the microdisk resonator, an external dielectric ring provided at an outer side of the microdisk resonator, and a transparent graphene electrode provided at upper surfaces of the microdisk resonator, the protruding dielectric ring and the external dielectric ring. Therefore, the processes required for generating a nanolaser may be reduced by half in comparison to a general technique, and a nanolaser may be generated just with a micro current.

Abstract: The present disclosure relates to a nanolaser generator using a transparent graphene electrode, a method for manufacturing the same, and a single nanopillar LED using the same. The nanolaser generator includes a microdisk resonator, a protruding dielectric ring provided to surround a boundary surface of the microdisk resonator, an external dielectric ring provided at an outer side of the microdisk resonator, and a transparent graphene electrode provided at upper surfaces of the microdisk resonator, the protruding dielectric ring and the external dielectric ring. Therefore, the processes required for generating a nanolaser may be reduced by half in comparison to a general technique, and a nanolaser may be generated just with a micro current.

Abstract: A dematrixing processor for an MPEG-2 multichannel audio decoder, which is capable of performing a decoding matrix process with respect to five compositely decoded signals to restore them to their original status. To this end, the dematrixing processor comprises an arithmetic/control logic unit for performing a dematrixing operation with respect to the five compositely decoded signals to restore them to their original status, and an IIR filter for low pass filtering an output signal from the arithmetic/control logic unit and providing the low pass filtered result to the arithmetic/control logic unit.

Abstract: A phase locked loop for synchronizing decoding clocks with encoding clocks in a Moving Picture Experts Group (MPEG) system. The phase-locked loop circuit includes a voltage controlled oscillator for converting a decoding clock into an encoding clock, a register unit for storing multiplexing program clock reference signals, each input with a desired number of bits, a counter being initialized by a first program clock reference signal output from the register unit, thereby generating a local program clock reference signal, and a phase error control unit for combinationally operating the program clock reference signal stored in the register unit and the local program clock reference signal, thereby generating a phase error signal for controlling the voltage controlled oscillator.

Abstract: The Centralized Management System utilizing a Bus Interface Unit comprises a Computer (4z) installing an address Bus (4a), data Bus (4b), and control Bus (4c), a First-Level Station (4Q1) communicating with the Computer (4z) as the First-Level Station (4Q1) is connected to the buses (4a, 4b, 4c) of the Computer (4z), a plurality of second-level stations (4Q2, 4Q3, . . . , 4QM) communicating with the First-Level Station (4Q1) as the second-level stations (4Q2, 4Q3, . . . , 4QM) are connected to the First-Level Station through a Multipoint Bus (4r). Therefore, the Centralized Management System is capable of communicating the Computer with the First-Level Station through a Dual Port RAM (Random Access Memory), intercommunicating a plurality of Second-Level Stations through a Multipoint Interface and Multipoint Bus, and controlling and managing several thousands of Terminals (for example, Public Telephones).

Abstract: A synthesis filter for an MPEG-2 audio decoder comprising a first coefficient ROM for storing cosine matrix coefficients therein, a first queue memory for storing subband data therein, a first MAC unit for performing a matrixing operation by multiplying the subband data stored in the first queue memory by the cosine matrix coefficients stored in the first coefficient ROM, a second queue memory for storing output data from the first MAC unit therein, a third queue memory being copied with the contents of the second queue memory, a second coefficient ROM for storing window coefficients therein, a second MAC unit for synthesizing the contents copied to the third queue memory with the window coefficients stored in the second coefficient ROM to produce audio data, an FIFO memory for storing the audio data from the second MAC unit therein, a D/A converter for converting the audio data stored in the FIFO memory into an analog audio signal and outputting the converted analog audio signal to a speaker, and a controlle

Abstract: A device and a method for performing a denormalization operation to restore channel signals, normalized into specified levels due to a multichannel process in an MPEG-2 multichannel audio decoder, to their original levels. The denormalization device performs the denormalization operation on the basis of one multiplication operation. To this end, the denormalization device comprises a ROM for storing therein denormalization information to be multiplied by data to be denormalized, a multiplier for multiplying the data to be denormalized, by the denormalization information stored in the ROM, and a controller for controlling the ROM and the multiplier.

Abstract: A very large scale integrated circuit for performing a bit-serial matrix transposition operation, comprising an input shift register module for inputting N multiplied results of two N.times.N matrixes in the unit of k bits and outputting them in the unit of k/N bits in response to a load signal, a bit-serial transposition module for selecting k/N-bit data from the input shift register module in response to a switching control signal, an output multiplexer module for selecting k/N-bit data from the bit-serial transposition module in response to the switching control signal, and an output register module for inputting output data from the output multiplexer module in the unit of k/N bits and outputting N data in the unit of k bits. According to the present invention, when an N.times.N matrix transposition operation is performed, the operation occupancy of transposition cells becomes 100% after an N-input delay occurs. Also, the processing unit of data becomes smaller by using a bit-serial processing algorithm.

Abstract: A composite decoding device for an MPEG-2 multichannel audio decoder. The composite decoding device is capable of simultaneously decoding information coded in a dynamic crosstalk coding manner and information coded in a phantom coding manner. To this end, the composite decoding device comprises an arithmetic unit for receiving a control word, information and a scale factor from a first-in-first-out memory, performing an arithmetic operation with respect to the received information and scale factor on the basis of a dynamic crosstalk coding manner or a phantom coding manner determined by the received control word and outputting the arithmetic result to a dual port memory, and a controller for generating a plurality of sequential control signals in response to the control word from the first-in-first-out memory to control the arithmetic unit.