Abstract: A semiconductor memory device includes a memory cell array and an input/output path circuit. The input/output path circuit performs an input/output line pre-charge operation at a write end time point and outputs data stored in the memory cell array when the semiconductor memory device is operated in a read mode.

Abstract: A circuit for generating a write data mask signal in a synchronous semiconductor memory device includes an output unit and a reset control unit. The output unit controls a write data mask operation of the synchronous semiconductor memory device, latches a write data mask signal, and outputs an internal write data mask signal, in response to an internal clock signal. The reset control unit generates a reset signal for resetting the internal write data mask signal, in response to a write column disable signal indicating an activation end point of a column selection line signal generated when a write operation including the write data mask operation is performed. While the synchronous semiconductor memory device performs a gapless write data mask operation included in a gapless write operation, the reset signal is deactivated so that the write data mask signal is not reset.

Abstract: A semiconductor memory device includes a memory cell array and an input/output path circuit. The input/output path circuit performs an input/output line pre-charge operation at a write end time point and outputs data stored in the memory cell array when the semiconductor memory device is operated in a read mode.

Abstract: A semiconductor memory device, a local precharge circuit and a method thereof are provided. The example semiconductor memory device may include a local input/output line connected to a bit line coupled with a memory cell, through a column selection transistor, the local input/output line providing a transmission path on which to transmit a data signal through the bit line to a local sense amplifier and a local precharge circuit configured to adjust a precharge voltage level of the local input/output line based on a status of an active mode and a status of a column selection signal. The active mode may be a period where a word line is enabled. The example local precharge circuit may be included within the example semiconductor memory device.

Abstract: Semiconductor memory devices, block select decoding circuits and a method of activating a word line are provided. An example semiconductor memory device may include a plurality of memory banks. Each of the plurality of memory banks may include memory blocks which may be arranged in different addressable orders. If two edge memory blocks are activated in a given one of the plurality of memory banks, a non-edge memory block may be concurrently activated in at least one of remaining memory banks other than the given one memory bank. Accordingly, a number of concurrently activated memory blocks, a voltage required to enable a word line and noise may be reduced. The example semiconductor device may include the example block select decoding circuit, and likewise may perform the example method of activating a word line with an activation of a reduced number of memory blocks.

Abstract: An internal voltage generator is highly tolerant of electrical parameter changes of transistors occurring due to process deviation. The generator can produce an internal voltage within a short setup time when there is a significant difference between a voltage level of an internal voltage when power is initially supplied to the internal voltage generator and a voltage level of an internal voltage to be produced. In one embodiment, the internal voltage generator of the present invention includes a comparator block and an output driving block to produce an internal voltage. The internal voltage generator further includes a reference voltage generation block, which generates at least two reference voltages to be supplied to the comparator block, and an offset section control block, which supplies a control signal for optimizing an offset section, that is, a voltage difference between the reference voltages, to the reference voltage generation block.

Abstract: A frequency regulator including a phase frequency detector and a lock detection unit. The phase frequency detector receives a reference signal and a feedback signal, compares a phase of the reference signal and a phase of the feedback signal, and outputs a first control signal and a second control signal to regulate phase and frequency of the feedback signal. The lock detection unit generates a phase lock signal in a case of keeping that a time difference between the first control signal and the second control signal is smaller than a reference time during an interval time period of at least a half period of the reference signal.

Abstract: A semiconductor memory device, a local precharge circuit and a method thereof are provided. The example semiconductor memory device may include a local input/output line connected to a bit line coupled with a memory cell, through a column selection transistor, the local input/output line providing a transmission path on which to transmit a data signal through the bit line to a local sense amplifier and a local precharge circuit configured to adjust a precharge voltage level of the local input/output line based on a status of an active mode and a status of a column selection signal. The example local precharge circuit may be included within the example semiconductor memory device. The example semiconductor memory device including the example local precharge circuit may be capable of adjusting a precharge voltage level of the local input/output line based on a status of an active mode and a status of a column selection signal, the active mode referring to a period where a word line is enabled.

Abstract: A circuit for generating a write data mask signal in a synchronous semiconductor memory device includes an output unit and a reset control unit. The output unit controls a write data mask operation of the synchronous semiconductor memory device, latches a write data mask signal, and outputs an internal write data mask signal, in response to an internal clock signal. The reset control unit generates a reset signal for resetting the internal write data mask signal, in response to a write column disable signal indicating an activation end point of a column selection line signal generated when a write operation including the write data mask operation is performed. While the synchronous semiconductor memory device performs a gapless write data mask operation included in a gapless write operation, the reset signal is deactivated so that the write data mask signal is not reset.

Abstract: Semiconductor memory devices, block select decoding circuits and a method of activating a word line are provided. An example semiconductor memory device may include a plurality of memory banks. Each of the plurality of memory banks may include memory blocks which may be arranged in different addressable orders. If two edge memory blocks are activated in a given one of the plurality of memory banks, a non-edge memory block may be concurrently activated in at least one of remaining memory banks other than the given one memory bank. Accordingly, a number of concurrently activated memory blocks, a voltage required to enable a word line and noise may be reduced. The example semiconductor device may include the example block select decoding circuit, and likewise may perform the example method of activating a word line with an activation of a reduced number of memory blocks.

Abstract: An internal voltage generator is highly tolerant of electrical parameter changes of transistors occurring due to process deviation. The generator can produce an internal voltage within a short setup time when there is a significant difference between a voltage level of an internal voltage when power is initially supplied to the internal voltage generator and a voltage level of an internal voltage to be produced. In one embodiment, the internal voltage generator of the present invention includes a comparator block and an output driving block to produce an internal voltage. The internal voltage generator further includes a reference voltage generation block, which generates at least two reference voltages to be supplied to the comparator block, and an offset section control block, which supplies a control signal for optimizing an offset section, that is, a voltage difference between the reference voltages, to the reference voltage generation block.