Abstract: A computational memory device and a method using the computational memory device are provided. The computational memory device includes memory banks configured to store weight data of a neural network model and a weight memory block configured to provide at least some of the weight data from memory banks in response to a weight request, a computational memory block physically stacked on the weight memory block such faces of the respective blocks face each other, the computational memory block configured to perform a multiply-accumulate (MAC) operation between the at least some of the weight data and at least some of input data by using a bit cell array including bit cells, and a communication interface configured to perform communication between the weight memory block and the computational memory block.

Abstract: A method and device with accelerator control are provided. The method includes monitoring instructions processed in a core processor, identifying a loop including at least one instruction as an acceleration target while monitoring, comparing at least one piece of information corresponding to the loop that is the acceleration target with information managed in a table, and based on a result of the comparison, identifying configuration information corresponding to the loop, the configuration information controlling connection status of connections among a plurality of process elements (PEs) included in an accelerator.

Abstract: A computational memory device and a method using the computational memory device are provided. The computational memory device includes memory banks configured to store weight data of a neural network model and a weight memory block configured to provide at least some of the weight data from memory banks in response to a weight request, a computational memory block physically stacked on the weight memory block such faces of the respective blocks face each other, the computational memory block configured to perform a multiply-accumulate (MAC) operation between the at least some of the weight data and at least some of input data by using a bit cell array including bit cells, and a communication interface configured to perform communication between the weight memory block and the computational memory block.

Abstract: Provided are a digital signal processor (DSP) and an electronic device using the same. The DSP includes: a first function unit (FU) having a non-IMC (in-memory computing) operation architecture using an operation unit; a second FU having an IMC architecture using a memory cell array; and a register file used by the first FU and the second FU.

Abstract: A neural network apparatus includes: a first processing circuit and a second processing circuit each configured to perform a vector-by-matrix multiplication (VMM) operation on a weight and an input activation; a first register configured to store an output of the first processing circuit; an adder configured to add an output of the first register and an output of the second processing circuit; a second register configured to store an output of the adder; and an input circuit configured to input a same input activation to the first processing circuit and the second processing circuit and control the first processing circuit and the second processing circuit.

Abstract: An in-register computing (IRC) device includes: a register module including a register bank and an addition device, the register bank including register cells, the register cells including IRC cells, wherein the register module is configured to allocate first of the register cells to an input area, second of the register cells to a weight area, and third of the register cells to an output area, wherein the input area is an area in which the register bank stores an input value, the weight area is an area including one of the IRC cells configured to perform an IRC operation between the input value and a weight value, and the output area is an area configured to store an output value obtained by performing an addition operation on an operation result of the IRC operation using an addition device.

Abstract: A neural network accelerator including always-on circuitry configured to determine pre-processed data, buffer circuitry including a plurality of banks configured to store the determined pre-processed data, and processor circuitry including a neural network model and configured to perform power-gating, the neural network model being configured to perform a neural network computation on the pre-processed data.

Abstract: A device including a memory array including N+1 resistive memory cells, the N+1 resistive memory cells including resistor values representing an N-bit sequence, the resistor values being determined based on a stuck resistor value of an error memory cell on a wordline including the error memory cell, the resistor values being set respectively and a write encoder configured to generate N+1 write signals respectively indicative of the resistor values to be set for the N+1 resistive memory cells, and N is an integer greater than or equal to 1.

Abstract: An in-memory computing (IMC) macro has a mode alternating between a first mode and a second mode, and the IMC macro includes: an input control circuit configured to be capable of generating a signal in which a predefined pattern is applied to an input signal and of transmitting a previous operation result that is fed back, and which is performed depends on which mode the operating mode is in; a crossbar array including memory cells including an additional row that processes and stores the fed-back previous operation result, and columns including an adder tree corresponding to the memory cells; and a post arithmetic circuit configured to be capable of performing a first operation corresponding to a spiking neural network (SNN) and a second operation corresponding to an artificial neural network (ANN), wherein which of the first and second operations is performed depends on which mode is in effect.

Abstract: A register file operator including a memory cell array, the memory cell array including plural subarrays configured to perform an operation between data stored in memory cells and input data, the plural subarrays which each include two read ports configured to read data as received data and a write port configured to write data as written data, and an operation circuit configured to output one or more of operation results of the memory cell array and pieces of the received data read through the two read ports.

Abstract: A non-volatile memory device includes a memory array including N+1 resistive memory cells expressing a bit sequence of N bits for each word line, in which N is an integer greater than or equal to 2.

Abstract: A processor-implemented method includes obtaining a benchmark execution result, receiving input data comprising a neural network model subject to prediction and analysis requirement information, receiving information on hardware of a device in which the neural network model is run, building a prediction model based on the benchmark execution result and the hardware information, extracting layer information respectively corresponding to a plurality of layers configuring the neural network model, and predicting either one or both of operation performance information and energy efficiency information respectively corresponding to the plurality of layers by inputting the analysis requirement information and the layer information to the prediction model.

Abstract: Provided are a digital signal processor (DSP) and an electronic device using the same. The DSP includes: a first function unit (FU) having a non-IMC (in-memory computing) operation architecture using an operation unit; a second FU having an IMC architecture using a memory cell array; and a register file used by the first FU and the second FU.

Abstract: A device includes: an operation module configured to store and operate a weight for an operation of a layer of a neural network model; a control module configured to generate setting information for performing the operation of the layer by the neural network model using the stored weight; an input module configured to receive input data for the operation of the layer based on the generated setting information; a merging module configured to receive operation results of the operation of the layer from the operation module and merge the received operation results of the layer; a post-processing module configured to receive the merged operation results of the layer from the merging module and post-process the received merged operation results of the layer; and an output stream module configured to convert and store the post-processed operation results based on the generated setting information.

Abstract: Disclosed is an in-memory computing device and method. The in-memory computing device includes: a memory unit including bit cells configured to store first input data having a reference-bit-count, receive second input data also having the reference-bit-count, and perform a multiplication operation between the first input data and the second input data; and an operation unit including: a first adder tree configured to output intermediate operation results by adding results of performing the multiplication operation output with respect to each of the bit cells; a branch module configured to branch the intermediate operation results according to an operation mode of the in-memory computing device; and a second adder tree configured to output a final operation result based on an output of the branch module.

Abstract: An electronic device and method with data scaling is provided herein. The electronic device may include a computing device that includes an analog computing circuit, where the computing device may scale an input of the analog computing circuit using a first scaling factor and/or scale a weight of the analog computing circuit using a second scaling factor, where the input includes a plurality of input values within a preset input maximum range of values of the computing device, and the weight includes a plurality of weight values within a preset weight maximum range of values of the computing device, and rescale an output of the analog computing circuit based on the first scaling factor and/or the second scaling factor. The first and second scaling factors may respectively scale values of the input and the weight to exceed respective preset maximum ranges of values.

Abstract: A memory device includes: a computing module; and an in-memory computing (IMC) macro comprising: a memory comprising a plurality of bit cells storing pieces of fraction data of a first data set; and an IMC computing module configured to perform an operation between the pieces of fraction data of the first data set read from the memory and pieces of fraction data of a second data set received from an input control module, wherein a plurality of pieces of data included in the first data set share a first exponent, and wherein a plurality of pieces of data included in the second data set share a second exponent.

Abstract: An apparatus includes a static random access memory (SRAM) cell including a first inverter and a second inverter, and a third inverter including a first inverter transistor and a second inverter transistor. An output terminal of the first inverter is connected to a source terminal of the second inverter transistor.

Abstract: A memory device includes: a computing module; and an in-memory computing (IMC) macro comprising: a memory comprising a plurality of bit cells storing pieces of fraction data of a first data set; and an IMC computing module configured to perform an operation between the pieces of fraction data of the first data set read from the memory and pieces of fraction data of a second data set received from an input control module, wherein a plurality of pieces of data included in the first data set share a first exponent, and wherein a plurality of pieces of data included in the second data set share a second exponent.

Abstract: Disclosed is an in memory computing (IMC) processor. An in memory computing (IMC) processor includes a static random access memory (SRAM) IMC device including type 1 IMC macros in which a direction of writing data therein is the same as an operation direction of performing a multiply and accumulate (MAC) operation in the type 1 IMC macros, and type 2 IMC macros in which a direction of writing data therein is different from the operation direction in the type 1 IMC macros, and the SRAM IMC device is configured to use the type 1 IMC macros and the type 2 IMC macros to perform a multiply and accumulation (MAC) operation between an input feature map and a weight, and a shift accumulator configured to perform a shift operation on an output of the SRAM IMC device and accumulate a result of the shift operation.