Abstract: A memory device includes: a computing module; and an in-memory computing (IMC) macro comprising: a memory comprising a plurality of bit cells storing pieces of fraction data of a first data set; and an IMC computing module configured to perform an operation between the pieces of fraction data of the first data set read from the memory and pieces of fraction data of a second data set received from an input control module, wherein a plurality of pieces of data included in the first data set share a first exponent, and wherein a plurality of pieces of data included in the second data set share a second exponent.

Abstract: An apparatus including a memory layer including a plurality of front-end-of-line (FEOL) memory cells and a logic layer including plural arithmetic logic gates including back-end-of-line (BEOL) transistors, the plurality of BEOL transistors being vertically stacked on respective upper ends of the plurality of memory cells, wherein each of multiple transistors of the plurality of BEOL transistors operates as a multiplier and is configured to provide an operation result with respect to first values stored in corresponding memory cells of the plurality of memory cells.

Abstract: Disclosed is an in memory computing (IMC) processor. An in memory computing (IMC) processor includes a static random access memory (SRAM) IMC device including type 1 IMC macros in which a direction of writing data therein is the same as an operation direction of performing a multiply and accumulate (MAC) operation in the type 1 IMC macros, and type 2 IMC macros in which a direction of writing data therein is different from the operation direction in the type 1 IMC macros, and the SRAM IMC device is configured to use the type 1 IMC macros and the type 2 IMC macros to perform a multiply and accumulation (MAC) operation between an input feature map and a weight, and a shift accumulator configured to perform a shift operation on an output of the SRAM IMC device and accumulate a result of the shift operation.

Abstract: A computational memory device and a method using the computational memory device are provided. The computational memory device includes memory banks configured to store weight data of a neural network model and a weight memory block configured to provide at least some of the weight data from memory banks in response to a weight request, a computational memory block physically stacked on the weight memory block such faces of the respective blocks face each other, the computational memory block configured to perform a multiply-accumulate (MAC) operation between the at least some of the weight data and at least some of input data by using a bit cell array including bit cells, and a communication interface configured to perform communication between the weight memory block and the computational memory block.

Abstract: Provided is a computation method of a memory processor configured to perform an operation between a first vector including first elements and a second vector including second elements, the first elements including respective first bits and the second elements including respective second bits, the method performed by the memory processor including: applying, to single-bit operation gates, the respective first bits and the respective second bits; obtaining bit operation result sum values for the respective first and second elements based on bit operation results obtained using the single-bit operation gates; and obtaining an operation result of the first vector and the second vector based on the bit operation result sum value.

Abstract: An apparatus and method with in-memory computing (IMC) are provided. An in-memory computing (IMC) circuit includes a plurality of memory banks, each memory bank including a bit cell configured to store a weight value and an operator configured to receive an input value, the operator being connected to the bit cell such that the operator upon receiving the input value outputs a logic operation result between the input value and the weight value, and a logic gate configured to receive the logic operation result of each of the memory banks.

Abstract: An in-memory computing (IMC) processor includes IMC macros, and includes a static random access memory (SRAM) IMC device including the plurality of IMC macros, and configured to perform a multiply and accumulate (MAC) operation between input data and first weight data of a first weight map applied to a first of IMC macros in a first direction in which an input feature map including the input data is written to the first IMC macro, and a two-dimensional (2D) shift accumulator configured to perform a shift operation on partial sums corresponding to respective MAC operation results of the IMC macros and accumulate a result of the shift operation.

Abstract: A neural network apparatus includes: a first processing circuit and a second processing circuit each configured to perform a vector-by-matrix multiplication (VMM) operation on a weight and an input activation; a first register configured to store an output of the first processing circuit; an adder configured to add an output of the first register and an output of the second processing circuit; a second register configured to store an output of the adder; and an input circuit configured to input a same input activation to the first processing circuit and the second processing circuit and control the first processing circuit and the second processing circuit.

Abstract: A device according to various embodiments may comprise: a transceiver unit configured to transmit or receive information; and a control unit operatively coupled to the transceiver unit, wherein the control unit may be configured to receive, from each of a plurality of control devices that transmit a request for data to a storage device, state information of each of the plurality of control devices, to determine a threshold value for an outstanding data request of each of the plurality of control devices on the basis of the received state information, and to transmit the threshold value to at least one other device.

Abstract: A device according to various embodiments may comprise: a transceiver unit configured to transmit or receive information; and a control unit operatively coupled to the transceiver unit, wherein the control unit may be configured to receive, from each of a plurality of control devices that transmit a request for data to a storage device, state information of each of the plurality of control devices, to determine a threshold value for an outstanding data request of each of the plurality of control devices on the basis of the received state information, and to transmit the threshold value to at least one other device.

Abstract: A mobile terminal and a method for managing a file system thereof are provided. The method of managing a file system of a mobile terminal having a battery cover and a battery cover coupling unit includes sensing an interruption of contact at a portion of a contact area between the battery cover and the battery cover coupling unit, generating a metadata list including metadata on data to be synchronized from among data cached in a volatile memory, after the sensing of the interruption of contact at the preset portion, sensing an interruption of contact at another portion of the contact area between the battery cover and the battery cover coupling unit after the previous sensing, and storing the metadata of the metadata list in a non-volatile memory, if the interval between the sensing operations is less than or equal to a threshold value.

Abstract: A method and apparatus for managing a virtual processor including resources for operating application through a real central processing unit, which includes determining a utilization of a plurality of real CPUs to which a plurality of virtual processors are divided to be allocated; and repartitioning the virtual processors and reallocating the repartitioned virtual processor to at least part of the real CPUs, when the utilization of any one of the real CPUs is at a threshold or less.

Abstract: A method and apparatus for controlling traffic of multiprocessor system or multi-core system is provided. The traffic control apparatus of a multiprocessor system according to the present invention includes a request handler for processing a traffic request of a first processor, and a Quality of Service (QoS) manager for receiving a QoS guaranty start instruction for a second processor from the multiprocessor system, and for transmitting, when traffic of the second processor is detected, a traffic adjustment signal to the request handler. The request handler adjusts the traffic of the first processor according to the received traffic adjustment signal. The traffic control method and apparatus of the present invention is capable of adjusting the required bandwidths of individual technologies and guaranteeing the real-timeness in the multiprocessor system or multi-core system.

Abstract: A mobile terminal and a method for managing a file system thereof are provided. The method of managing a file system of a mobile terminal having a battery cover and a battery cover coupling unit includes sensing an interruption of contact at a portion of a contact area between the battery cover and the battery cover coupling unit, generating a metadata list including metadata on data to be synchronized from among data cached in a volatile memory, after the sensing of the interruption of contact at the preset portion, sensing an interruption of contact at another portion of the contact area between the battery cover and the battery cover coupling unit after the previous sensing, and storing the metadata of the metadata list in a non-volatile memory, if the interval between the sensing operations is less than or equal to a threshold value.

Abstract: A method and apparatus for controlling traffic of multiprocessor system or multi-core system is provided. The traffic control apparatus of a multiprocessor system according to the present invention includes a request handler for processing a traffic request of a first processor, and a Quality of Service (QoS) manager for receiving a QoS guaranty start instruction for a second processor from the multiprocessor system, and for transmitting, when traffic of the second processor is detected, a traffic adjustment signal to the request handler. The request handler adjusts the traffic of the first processor according to the received traffic adjustment signal. The traffic control method and apparatus of the present invention is capable of adjusting the required bandwidths of individual technologies and guaranteeing the real-timeness in the multiprocessor system or multi-core system.

Abstract: A method and apparatus for managing a virtual processor including resources for operating application through a real central processing unit, which includes determining a utilization of a plurality of real CPUs to which a plurality of virtual processors are divided to be allocated; and repartitioning the virtual processors and reallocating the repartitioned virtual processor to at least part of the real CPUs, when the utilization of any one of the real CPUs is at a threshold or less.

Abstract: A method for performing verification on a Transaction Level (TL) model having at least two abstraction levels in simulation modeling for design of a System-on-Chip (SoC). The TL model verification method includes acquiring first request information and first response information; acquiring second request information and second response information; dividing the first and second request information and the first and second response information; comparing the divided first and second request information and comparing the divided first and second response information; and verifying a modeling result on the TL model depending on the comparison results.

Abstract: A method for performing verification on a Transaction Level (TL) model having at least two abstraction levels in simulation modeling for design of a System-on-Chip (SoC). The TL model verification method includes acquiring first request information and first response information; acquiring second request information and second response information; dividing the first and second request information and the first and second response information; comparing the divided first and second request information and comparing the divided first and second response information; and verifying a modeling result on the TL model depending on the comparison results.