Abstract: A method of forming a thin ruthenium-containing layer includes performing a CVD process using butyl ruthenoscene as a ruthenium source material. The thin ruthenium-containing layer may be formed by a one-step or two-step CVD process. The one-step CVD process is performed under a constant oxygen flow rate and a constant deposition pressure. The two-step CVD process includes forming a seed layer and forming a main layer, each of which is performed under a different process condition of a deposition temperature, an oxygen flow rate, and a deposition pressure.

Abstract: A method of forming a thin ruthenium-containing layer includes performing a CVD process using butyl ruthenoscene as a ruthenium source material. The thin ruthenium-containing layer may be formed by a one-step or two-step CVD process. The one-step CVD process is performed under a constant oxygen flow rate and a constant deposition pressure. The two-step CVD process includes forming a seed layer and forming a main layer, each of which is performed under a different process condition of a deposition temperature, an oxygen flow rate, and a deposition pressure.

Abstract: The effective area of a MIM capacitor is increased by forming a lower electrode that includes hemispherical grain lumps. The hemispherical grain lumps are formed by heat-treating a metal layer in an oxygen and/or nitrogen atmosphere, thus oxidizing the surface of the metal layer or growing the crystal grains of the metal layer. The MIM capacitor may be formed of Pt, Ru, Rh, Os, Ir, or Pd, and the hemispherical grain lumps may be formed of Pt, Ru, Rh, Os, Ir, or Pd. Since the metal layer is primarily heat-treated during the formation of the lower electrode, it is possible to reduce the degree to which the surface morphology of the lower electrode is rapidly changed due to a heat treatment subsequent to forming a dielectric layer and an upper electrode.

Abstract: A method for fabricating a semiconductor device is provided. The method includes the steps of: forming an insulating layer having an opening region on a semiconductor substrate; forming a first ruthenium layer on the insulating layer and the opening region by sputtering at a first pressure; forming a second ruthenium layer on the first ruthenium layer by first chemical vapor deposition (CVD) at a first flow rate of oxygen gas and at a second pressure, wherein the second pressure is greater than the first pressure; and forming a third ruthenium layer on the second ruthenium layer by second CVD at a second flow rate of oxygen gas and at a third pressure, wherein the third pressure is greater than the first pressure.

Abstract: A layer is formed by chemical vapor depositing a seeding layer of ruthenium oxide on a substrate at a chemical vapor deposition flow rate ratio of a ruthenium source to oxygen gas. A main layer of ruthenium is chemical vapor deposited on the seeding layer by increasing the chemical vapor deposition flow rate ratio of the ruthenium source to the oxygen gas.

Abstract: The effective area of a MIM capacitor is increased by forming a lower electrode that includes hemispherical grain lumps. The hemispherical grain lumps are formed by heat-treating a metal layer in an oxygen and/or nitrogen atmosphere, thus oxidizing the surface of the metal layer or growing the crystal grains of the metal layer. The MIM capacitor may be formed of Pt, Ru, Rh, Os, Ir, or Pd, and the hemispherical grain lumps may be formed of Pt, Ru, Rh, Os, Ir, or Pd. Since the metal layer is primarily heat-treated during the formation of the lower electrode, it is possible to reduce the degree to which the surface morphology of the lower electrode is rapidly changed due to a heat treatment subsequent to forming a dielectric layer and an upper electrode.

Abstract: A dielectric region for a device such as a memory cell capacitor is formed by depositing a metal oxide, such as tantalum oxide, on a substrate at a first deposition rate in a first atmosphere maintained within a first temperature range and a first pressure range that produce a first tantalum oxide layer with a desirable step coverage. Metal oxide is subsequently deposited on the first metal oxide layer in a second atmosphere maintained within a second temperature range and a second pressure range that produce a second deposition rate greater than the first deposition rate to form a second tantalum oxide layer on the first tantalum oxide layer. For example, the first atmosphere may be maintained at a temperature in a range from about 350° C. to about 460° C. and a pressure in a range from about 0.01 Torr to about 2.0 Torr during formation of a first tantalum oxide layer, and the second atmosphere may be maintained at a temperature in a range from about 400° C. to about 500° C.

Abstract: A method of forming a thin ruthenium-containing layer includes performing a CVD process using butyl ruthenoscene as a ruthenium source material. The thin ruthenium-containing layer may be formed by a one-step or two-step CVD process. The one-step CVD process is performed under a constant oxygen flow rate and a constant deposition pressure. The two-step CVD process includes forming a seed layer and forming a main layer, each of which is performed under a different process condition of a deposition temperature, an oxygen flow rate, and a deposition pressure.

Abstract: A method for fabricating a semiconductor device is provided. The method includes the steps of: forming an insulating layer having an opening region on a semiconductor substrate; forming a first ruthenium layer on the insulating layer and the opening region by sputtering at a first pressure; forming a second ruthenium layer on the first ruthenium layer by first chemical vapor deposition (CVD) at a first flow rate of oxygen gas and at a second pressure, wherein the second pressure is greater than the first pressure; and forming a third ruthenium layer on the second ruthenium layer by second CVD at a second flow rate of oxygen gas and at a third pressure, wherein the third pressure is greater than the first pressure.

Abstract: The effective area of a MIM capacitor is increased by forming a lower electrode that includes hemispherical grain lumps. The hemispherical grain lumps are formed by heat-treating a metal layer in an oxygen and/or nitrogen atmosphere, thus oxidizing the surface of the metal layer or growing the crystal grains of the metal layer. The MIM capacitor may be formed of Pt, Ru, Rh, Os, Ir, or Pd, and the hemispherical grain lumps may be formed of Pt, Ru, Rh, Os, Ir, or Pd. Since the metal layer is primarily heat-treated during the formation of the lower electrode, it is possible to reduce the degree to which the surface morphology of the lower electrode is rapidly changed due to a heat treatment subsequent to forming a dielectric layer and an upper electrode.

Abstract: A method for manufacturing a capacitor of a semiconductor memory device by a two-step thermal treatment is provided. A lower electrode is formed on a semiconductor substrate. A dielectric layer is formed over the lower electrode. An upper electrode formed of a noble metal is formed over the dielectric layer. The resultant having the upper electrode undergoes a first thermal treatment under a first atmosphere including oxygen at a first temperature which is selected to be within a range of 200-600° C., which is lower than the oxidation temperature of the upper electrode. The first thermally treated resultant undergoes a second thermal treatment under a second atmosphere without oxygen at a second temperature which is selected to be within a range of 300-900° C., which is higher than the first temperature.

Abstract: A layer is formed by chemical vapor depositing a seeding layer of ruthenium oxide on a substrate at a chemical vapor deposition flow rate ratio of a ruthenium source to oxygen gas. A main layer of ruthenium is chemical vapor deposited on the seeding layer by increasing the chemical vapor deposition flow rate ratio of the ruthenium source to the oxygen gas.

Abstract: A method for manufacturing a capacitor of a semiconductor memory device by a two-step thermal treatment is provided. A lower electrode is formed on a semiconductor substrate. A dielectric layer is formed over the lower electrode. An upper electrode formed of a noble metal is formed over the dielectric layer. The resultant having the upper electrode undergoes a first thermal treatment under a first atmosphere including oxygen at a first temperature which is selected to be within a range of 200-600° C., which is lower than the oxidation temperature of the upper electrode. The first thermally treated resultant undergoes a second thermal treatment under a second atmosphere without oxygen at a second temperature which is selected to be within a range of 300-900° C., which is higher than the first temperature.

Abstract: A dielectric region for a device such as a memory cell capacitor is formed by depositing a metal oxide, such as tantalum oxide, on a substrate at a first deposition rate in a first atmosphere maintained within a first temperature range and a first pressure range that produce a first tantalum oxide layer with a desirable step coverage. Metal oxide is subsequently deposited on the first metal oxide layer in a second atmosphere maintained within a second temperature range and a second pressure range that produce a second deposition rate greater than the first deposition rate to form a second tantalum oxide layer on the first tantalum oxide layer. For example, the first atmosphere may be maintained at a temperature in a range from about 350° C. to about 460° C. and a pressure in a range from about 0.01 Torr to about 2.0 Torr during formation of a first tantalum oxide layer, and the second atmosphere may be maintained at a temperature in a range from about 400° C. to about 500° C.