Abstract: Disclosed is an operating method of an electronic device which includes a processor executing a semiconductor layout simulation module based on machine learning. The operating method includes receiving, at the semiconductor layout simulation module executed by the processor, a layout image, inferring a wafer image based on the layout image and a fabrication device information image of a semiconductor fabrication device fabricating a semiconductor integrated circuit based on a final layout image, adjusting the layout image when the wafer image is not acceptable, and confirming the layout image as the final layout image when the wafer image is acceptable.

Abstract: The inventive concept provides a corner rounding method of a deep learning-based optical proximity correction (OPC) pattern by which patterning reliability may be ensured, and an OPC method and a mask manufacturing including the corner rounding method. The corner rounding method of a deep learning-based OPC pattern includes: obtaining a contour of a photoresist (PR) pattern or an etching pattern on a wafer; obtaining a square layout of the PR pattern or the etching pattern corresponding to the contour; generating a transform model through deep learning with the square layout and the contour; and obtaining a rounded layout target with respect to a square layout target by using the transform model.

Abstract: Disclosed is a semiconductor integrated circuit fabricating method of a semiconductor fabricating device which includes a processor executing a defect detection module includes receiving, at the defect detection module, a first capture image of the semiconductor integrated circuit and a first layout image, generating, at the defect detection module, a second layout image from the first capture image, generating, at the defect detection module, a contour image from the first capture image and the second layout image, detecting, at the defect detection module, a defect of the semiconductor integrated circuit based on the first layout image and the contour image, analyzing, at the semiconductor fabricating device, a correlation between a kind of the defect and process variations of the semiconductor integrated circuit, and changing, at the semiconductor fabricating device, at least one process variation having a correlation with the defect from among the process variations.

Abstract: A semiconductor device patterning method includes generating an input image by imaging information about a pattern of a sample, acquiring an output image of the pattern of the sample after a preset semiconductor process with respect to the sample, generating a predictive model through learning using a Deep Neural Network (DNN) with the input image and the output image, and predicting a pattern image after the semiconductor process for a pattern of a semiconductor device by using the predictive model.

Abstract: An operating method of a computing device for predicting a profile using deep learning includes sampling a unique pattern in a full chip, extracting a contour of a resist profile of each of a plurality of heights by performing rigorous simulation corresponding to the unique pattern, preparing an input image and an output image corresponding to the contour of each of the plurality of heights, performing deep learning on the extracted contour using the input image and the output image, and generating a profile prediction model according to performing of the deep leaning.

Abstract: A method of training a semiconductor process image generator includes training the semiconductor process image generator with a plurality of mask images including a first group and a second group, training the semiconductor process image generator with the second group and a first transformed group obtained by applying a transformation to the first group, and training the semiconductor process image generator with the first group and a second transformed group obtained by applying a transformation to the second group.

Abstract: The inventive concept provides a defect detection method of a semiconductor element, capable of promptly and accurately detecting a defect, and predicting a type of the defect with respect to various defects of the semiconductor element, and a semiconductor element manufacturing method including the defect detection method. The defect detection method is capable of promptly and accurately detecting the defect, and predicting the type of the defect with respect to various defects of the semiconductor element, by generating a first segmentation image and a second segmentation image; converting the first segmentation image and the second segmentation image into an image of a first color and a second color, respectively; generating a combination image; classifying the type of a defect; generating a defect detection model by using deep learning, and detecting a defect of the semiconductor element by using a defect detection process using the defect detection model.

Abstract: Disclosed are a method of forming an optical proximity correction (OPC) model and/or a method of fabricating a semiconductor device using the same. The method of forming the OPC model may include obtaining a scanning electron microscope (SEM) image, which is an average image of a plurality of images taken using one or more scanning electron microscopes, and a graphic data system (GDS) image, which is obtained by imaging a designed layout, aligning the SEM image and the GDS image, performing an image filtering process on the SEM image, extracting a contour from the SEM image, and verifying the contour. The verifying of the contour may be performed using a genetic algorithm. Variables in the genetic algorithm may include first parameters related to the image alignment process, second parameters related to the image filtering process, and third parameters related to a critical dimension (CD) measurement process.

Abstract: A method for correcting a mask layout includes providing a mask layout including first patterns, each of the first patterns having a size related to a first critical dimension (CD) value, obtaining topography data on a region of a wafer, generating a defocus map using the topography data, and correcting the mask layout on the basis of the defocus map. The generating of the defocus map includes respectively setting second CD values for a plurality of sub-regions of the mask layout. The second CD values may be set based on the topography data. The correcting of the mask layout on the basis of the defocus map comprises correcting the sizes of the first patterns to be related to the second CD values.

Abstract: A method for correcting a mask layout includes providing a mask layout including first patterns, each of the first patterns having a size related to a first critical dimension (CD) value, obtaining topography data on a region of a wafer, generating a defocus map using the topography data, and correcting the mask layout on the basis of the defocus map. The generating of the defocus map includes respectively setting second CD values for a plurality of sub-regions of the mask layout. The second CD values may be set based on the topography data. The correcting of the mask layout on the basis of the defocus map comprises correcting the sizes of the first patterns to be related to the second CD values.

Abstract: One embodiment of the present invention provides a system that adjusts assist features in a layout to prevent assist features from printing. During operation, the system receives a layout. The system then identifies an assist-feature (AF)-printing hotspot in the layout, wherein the AF-printing hotspot includes a set of assist features and one or more target patterns in proximity to the set of assist features. At least one assist feature in the set of assist features is expected to print during a lithography process. Next, the system modifies the AF-printing hotspot by: (1) modifying the set of assist features; and (2) performing optical-proximity-correction (OPC) on the one or more target patterns. The system then performs a lithography simulation on the modified AF-printing hotspot to determine if: (1) a through-process-window associated with the modified AF-printing hotspot is acceptable; and (2) no assist feature in the modified set of assist features is expected to print.

Abstract: One embodiment of the present invention provides a system that adjusts assist features in a layout to prevent assist features from printing. During operation, the system receives a layout. The system then identifies an assist-feature (AF)-printing hotspot in the layout, wherein the AF-printing hotspot includes a set of assist features and one or more target patterns in proximity to the set of assist features. At least one assist feature in the set of assist features is expected to print during a lithography process. Next, the system modifies the AF-printing hotspot by: (1) modifying the set of assist features; and (2) performing optical-proximity-correction (OPC) on the one or more target patterns. The system then performs a lithography simulation on the modified AF-printing hotspot to determine if: (1) a through-process-window associated with the modified AF-printing hotspot is acceptable; and (2) no assist feature in the modified set of assist features is expected to print.