Patents by Inventor Soo-Woong AHN
Soo-Woong AHN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11955458Abstract: Disclosed is a semiconductor package comprising a logic die mounted on an interposer substrate, and a memory stack structure disposed side-by-side with the logic die. The memory stack structure includes a buffer die mounted on the interposer substrate, and a plurality of memory dies stacked on the buffer die. The buffer die has a first surface that faces the interposer substrate and a second surface that faces the plurality of memory dies. The number of data terminals on the second surface is greater the number of connection terminals on the first surface.Type: GrantFiled: May 17, 2023Date of Patent: April 9, 2024Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sangkil Lee, So-young Kim, Soo-woong Ahn
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Publication number: 20230290754Abstract: Disclosed is a semiconductor package comprising a logic die mounted on an interposer substrate, and a memory stack structure disposed side-by-side with the logic die. The memory stack structure includes a buffer die mounted on the interposer substrate, and a plurality of memory dies stacked on the buffer die. The buffer die has a first surface that faces the interposer substrate and a second surface that faces the plurality of memory dies. The number of data terminals on the second surface is greater the number of connection terminals on the first surface.Type: ApplicationFiled: May 17, 2023Publication date: September 14, 2023Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sangkil LEE, So-young Kim, Soo-woong Ahn
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Patent number: 11688719Abstract: Disclosed is a semiconductor package comprising a logic die mounted on an interposer substrate, and a memory stack structure disposed side-by-side with the logic die. The memory stack structure includes a buffer die mounted on the interposer substrate, and a plurality of memory dies stacked on the buffer die. The buffer die has a first surface that faces the interposer substrate and a second surface that faces the plurality of memory dies. The number of data terminals on the second surface is greater the number of connection terminals on the first surface.Type: GrantFiled: January 14, 2022Date of Patent: June 27, 2023Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sangkil Lee, So-young Kim, Soo-woong Ahn
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Patent number: 11409676Abstract: Provided is a SoC, a memory device, an electronic device and a method for storing data in an electronic device. The electronic device comprises a host configured to output data, and a memory device including a memory storage configured to receive the data and to store the data. The host is configured to generate data bus inversion (DBI) information on the data to be provided to the memory device in accordance with a data parallelizing system, the data parallelizing system being inside the memory device, and to provide the DBI information to the memory device. The memory device is configured to provide the data to the memory storage, the data output from the host, the data encoded in accordance with the DBI information, the providing the data being in accordance with the data parallelizing system.Type: GrantFiled: September 10, 2020Date of Patent: August 9, 2022Assignee: Samsung Electronics Co., Ltd.Inventors: Ji Hyun Choi, Hyun-Joong Kim, Joon Sik Sohn, Woong-Jae Song, Soo-Woong Ahn, Seung-Hyun Cho
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Publication number: 20220139875Abstract: Disclosed is a semiconductor package comprising a logic die mounted on an interposer substrate, and a memory stack structure disposed side-by-side with the logic die. The memory stack structure includes a buffer die mounted on the interposer substrate, and a plurality of memory dies stacked on the buffer die. The buffer die has a first surface that faces the interposer substrate and a second surface that faces the plurality of memory dies. The number of data terminals on the second surface is greater the number of connection terminals on the first surface.Type: ApplicationFiled: January 14, 2022Publication date: May 5, 2022Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sangkil Lee, So-young Kim, Soo-woong Ahn
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Patent number: 11251155Abstract: Disclosed is a semiconductor package comprising a logic die mounted on an interposer substrate, and a memory stack structure disposed side-by-side with the logic die. The memory stack structure includes a buffer die mounted on the interposer substrate, and a plurality of memory dies stacked on the buffer die. The buffer die has a first surface that faces the interposer substrate and a second surface that faces the plurality of memory dies. The number of data terminals on the second surface is greater the number of connection terminals on the first surface.Type: GrantFiled: November 20, 2019Date of Patent: February 15, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sangkil Lee, So-young Kim, Soo-woong Ahn
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Publication number: 20210182223Abstract: Provided is a SoC, a memory device, an electronic device and a method for storing data in an electronic device. The electronic device comprises a host configured to output data, and a memory device including a memory storage configured to receive the data and to store the data. The host is configured to generate data bus inversion (DBI) information on the data to be provided to the memory device in accordance with a data parallelizing system, the data parallelizing system being inside the memory device, and to provide the DBI information to the memory device. The memory device is configured to provide the data to the memory storage, the data output from the host, the data encoded in accordance with the DBI information, the providing the data being in accordance with the data parallelizing system.Type: ApplicationFiled: September 10, 2020Publication date: June 17, 2021Applicant: Samsung Electronics Co., Ltd.Inventors: Ji Hyun CHOI, Hyun-Joong KIM, Joon Sik SOHN, Woong-Jae SONG, Soo-Woong AHN, Seung-Hyun CHO
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Publication number: 20200381393Abstract: Disclosed is a semiconductor package comprising a logic die mounted on an interposer substrate, and a memory stack structure disposed side-by-side with the logic die. The memory stack structure includes a buffer die mounted on the interposer substrate, and a plurality of memory dies stacked on the buffer die. The buffer die has a first surface that faces the interposer substrate and a second surface that faces the plurality of memory dies. The number of data terminals on the second surface is greater the number of connection terminals on the first surface.Type: ApplicationFiled: November 20, 2019Publication date: December 3, 2020Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sangkil LEE, So-young KIM, Soo-woong AHN
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Patent number: 9891856Abstract: A memory system includes an address remapping circuit and a first set of memory devices. The address remapping circuit includes a plurality of input terminals for receiving a plurality of chip selection signals and a plurality of chip identification signals. The address remapping circuit receives input signals corresponding to a portion of the plurality of chip selection signals and the plurality of chip identification signals through corresponding input terminals of the plurality of input terminals and generates a plurality of internal chip selection signals based on the input signals and a remapping control signal. Each of the first set of memory devices is configured to be selected in response to a corresponding internal chip selection signal of the plurality of internal chip selection signals.Type: GrantFiled: November 30, 2015Date of Patent: February 13, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Won-Hyung Song, Duk-Sung Kim, Hoki Kim, Soo-Woong Ahn, Ha-Ryong Yoon, Ju-Yun Jung
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Publication number: 20160162217Abstract: A memory system includes an address remapping circuit and a first set of memory devices. The address remapping circuit includes a plurality of input terminals for receiving a plurality of chip selection signals and a plurality of chip identification signals. The address remapping circuit receives input signals corresponding to a portion of the plurality of chip selection signals and the plurality of chip identification signals through corresponding input terminals of the plurality of input terminals and generates a plurality of internal chip selection signals based on the input signals and a remapping control signal. Each of the first set of memory devices is configured to be selected in response to a corresponding internal chip selection signal of the plurality of internal chip selection signals.Type: ApplicationFiled: November 30, 2015Publication date: June 9, 2016Inventors: Won-Hyung SONG, Duk-Sung KIM, Hoki KIM, Soo-Woong AHN, Ha-Ryong YOON, Ju-Yun JUNG