Abstract: A bitline sense amplifier including: an amplifier which is connected between a first sensing bitline and a second sensing bitline, and detects and amplifies a voltage difference between a first bitline and a second bitline in response to a first control signal and a second control signal; and an equalizer which is connected between a first supply line through which the first control signal is supplied and a second supply line through which the second control signal is supplied, and pre-charges the first bitline and the second bitline with a precharge voltage in response to an equalizing control signal, wherein the equalizer includes an equalizing enable transistor in which a source terminal is connected to the first supply line and performs equalizing in response to the equalizing control signal.

Abstract: A display panel includes pixels connected to first and second data lines and a readout line. The data driver supplies data signals to the first and second data lines and supplies an initialization voltage to the readout line. Each of the pixels includes at least one light emitting element and a driving transistor. The driving transistor controls an amount of current based on a difference between a corresponding data signal among the data signals and an initialization voltage. In a sensing mode, the data driver supplies a test voltage to the first data line and a first off voltage to the second data line in a first period and supplies a second off voltage to the second data line in a second period after the first period. The second off voltage is different from the test voltage and the first off voltage.

Abstract: A display device includes a pixel electrically connected to a first gate line and a second gate line and disposed in a first row, a pixel electrically connected to the second gate line and a reset line and disposed in a second row after the first row, a pixel electrically connected to a third gate line and a fourth gate line and disposed in a third row after the second row, and a gate driver supplying first to fourth gate signals to the first to fourth gate lines and supplying a reset signal to the reset line. The gate driver supplies the reset signal and the third gate signal of a same timing during an active period, and supplies the reset signal having a high level and the third gate signal having a low level during a rest period.

Abstract: A display device includes a display panel including data lines and pixels electrically connected to the data lines. The data driver supplies data signals to the data lines. The data driver includes: a first output buffer electrically connected to a first data line of the data lines, the first output buffer outputting a first data signal to the first data line; and a first comparator electrically connected to an output terminal of the first output buffer, the first comparator comparing a first slew rate of the first data signal with a first reference slew rate.

Abstract: Provided is a vector library for yeast two-hybrid screening of a deubiquitinating enzyme that binds to a target protein and a method for identifying a deubiquitinating enzyme binding to a target protein using the same. Further provided is a method for screening an agent having anti-cancer activity targeting the deubiquitinating enzyme USP1, USP7, USP12, or USP49 identified by the identifying method.

Abstract: A flexible film includes first input pad parts and second input pad parts, first output pad parts corresponding to the first input pad parts and second output pad parts corresponding to the second input pad parts, a first voltage line supplying a first voltage received from the first input pad parts to the first output pad parts, and a second voltage line supplying a second voltage received from the second input pad parts and the second voltage being lower than the first voltage to the second output pad parts. The first voltage line includes first vertical voltage lines electrically connected between the first input pad parts and the first output pad parts, and first horizontal voltage lines electrically connecting adjacent first vertical voltage lines of the first vertical voltage lines to each other.

Abstract: A display device includes: a display panel including pixels, first to N-th gate integrated circuits (GICs) embedded in gate circuit boards and configured to output gate signals to the pixels, a first gate input power line and a first gate input signal line formed to pass through the gate circuit boards and connected to the GICs, a first feedback power line connected to the first gate input power line, a power supply configured to output a first gate input voltage to the first gate input power line, a first compensator configured to output a first compensation signal in response to a first feedback voltage from the first feedback power line, and a controller configured to output a first gate control signal to the first gate input signal line and output a power control signal to the power supply in response to the first compensation signal.

Abstract: The present invention provides a vector library for yeast two-hybrid screening of a deubiquitinating enzyme that binds to a target protein and a method for identifying a deubiquitinating enzyme binding to a target protein using the same. Also, the present invention provides a method for screening an agent having anti-cancer activity targeting the deubiquitinating enzyme USP1, USP7, USP12, or USP49 identified by said identifying method.

Abstract: A display device includes a display panel including data lines, line capacitors respectively connected to the data lines, and pixels receiving a data voltage from the data lines, and a data driver supplying the data voltage to the pixels through the data lines and supplying different charging voltages respectively to the line capacitors through the data line. The data driver senses voltage change of at least one of the data lines occurring in case that at least one of the line capacitors is charged or discharged.

Abstract: A display device includes a display panel including a plurality of pixels, a controller for providing a clock-embedded data signal including image data in an active period and including a training pattern in a blank period, and a data driver for recovering the image data from the clock-embedded data signal based on an internal clock signal to provide data voltages corresponding to the image data to the plurality of pixels in the active period, and to perform a training operation for the internal clock signal using the training pattern included in the clock-embedded data signal in the blank period. The training pattern in the blank period includes a first training clock signal modulated with a first modulation period during a first time, and includes a second training clock signal modulated with a second modulation period different from the first modulation period after the first time.

Abstract: A display device includes a display panel including a pixel including a light emitting element emitting light and electrically connected to a data line and a sensing line, a timing controller varying a driving frequency of the display panel based on an input frequency of digital video data, and a data driver supplying a data voltage to the data line based on the digital video data during a data addressing period of a frame period and receiving a sensing signal from the sensing line during a sensing period. The data driver electrically connects the sensing line to an initialization voltage line during the data addressing period in case that the digital video data is changed, and electrically connects the sensing line to a high impedance during the data addressing period in case that the digital video data is not changed.

Abstract: A display panel includes pixels connected to first and second data lines and a readout line. The data driver supplies data signals to the first and second data lines and supplies an initialization voltage to the readout line. Each of the pixels includes at least one light emitting element and a driving transistor. The driving transistor controls an amount of current based on a difference between a corresponding data signal among the data signals and an initialization voltage. In a sensing mode, the data driver supplies a test voltage to the first data line and a first off voltage to the second data line in a first period and supplies a second off voltage to the second data line in a second period after the first period. The second off voltage is different from the test voltage and the first off voltage.

Abstract: A display device includes: a plurality of pixels coupled to data lines and sensing lines; a data driver configured to supply one of an image data signal and a sensing data signal to the data lines; a voltage supply configured to supply an initialization voltage to the pixels through the sensing lines; and a sensing circuit configured to receive a sensing value from at least one of the pixels through the sensing lines, and compare the sensing value with a sensing reference value to generate a sensing voltage control signal to control at least one of the sensing data signal or the initialization voltage.

Abstract: A display device includes a display panel including data lines and pixels electrically connected to the data lines. The data driver supplies data signals to the data lines. The data driver includes: a first output buffer electrically connected to a first data line of the data lines, the first output buffer outputting a first data signal to the first data line; and a first comparator electrically connected to an output terminal of the first output buffer, the first comparator comparing a first slew rate of the first data signal with a first reference slew rate.

Abstract: A display device includes pixels; a sensing block generating first sensing data during a first sensing period, and generating second sensing data and third sensing data during a second sensing period; and a timing controller compensating first image data with second image data based on the first sensing data, the second sensing data, and the third sensing data. The sensing block generates the first sensing data corresponding to an initial channel voltage applied to each of sensing channels and at least one auxiliary sensing channel during the first sensing period, generates the second sensing data by sensing characteristic information of the pixels corresponding to an initialization voltage applied to the pixels during the second sensing period, and generates the third sensing data corresponding to a reference voltage applied to the at least one auxiliary sensing channel during the second sensing period.

Abstract: A display device includes: a display panel including pixels, first to N-th gate integrated circuits (GICs) embedded in gate circuit boards and configured to output gate signals to the pixels, a first gate input power line and a first gate input signal line formed to pass through the gate circuit boards and connected to the GICs, a first feedback power line connected to the first gate input power line, a power supply configured to output a first gate input voltage to the first gate input power line, a first compensator configured to output a first compensation signal in response to a first feedback voltage from the first feedback power line, and a controller configured to output a first gate control signal to the first gate input signal line and output a power control signal to the power supply in response to the first compensation signal.

Abstract: A display device includes a display panel including a pixel including a light emitting element emitting light and electrically connected to a data line and a sensing line, a timing controller varying a driving frequency of the display panel based on an input frequency of digital video data, and a data driver supplying a data voltage to the data line based on the digital video data during a data addressing period of a frame period and receiving a sensing signal from the sensing line during a sensing period. The data driver electrically connects the sensing line to an initialization voltage line during the data addressing period in case that the digital video data is changed, and electrically connects the sensing line to a high impedance during the data addressing period in case that the digital video data is not changed.

Abstract: A brain computer interface (BCI) system predicts text based on input and output signals obtained in relation to an individual that are informative for determining an individual's neurobiological activity. The BCI system applies a first predictive model to the input signal and a second predictive model to the output signal. The first predictive model predicts the forward propagation of the input signal through the individual's head whereas the second predictive model predicts the backward propagation of the output signal through the individual's head. Each of the first predictive model and second predictive model predicts characteristics of their respective signal at a common plane such as the cortical surface of the individual's brain. The BCI system predicts text by applying a third predictive model to the predicted signal characteristics at the common plane outputted by the first predictive model and the second predictive model.

Abstract: Embodiments relate to a brain computer interface (BCI) including a light source subsystem, an interface transmitting light from the light source subsystem to a body region of a user, and a detector subsystem coupled to the interface and configured to receive light signals from the body region of the user. The light source subsystem, the interface, and the detector subsystem are coupled to other electronics providing power, computing functionality, and/or other functionality. The BCI is designed to be worn at a head region of a user and to generate optical signals that can be used to characterize brain activity of the user, where decoded brain activity can be used as inputs to control other systems and/or electronic content provided to the user.

Abstract: A display device includes a display panel including a plurality of pixels, a controller for providing a clock-embedded data signal including image data in an active period and including a training pattern in a blank period, and a data driver for recovering the image data from the clock-embedded data signal based on an internal clock signal to provide data voltages corresponding to the image data to the plurality of pixels in the active period, and to perform a training operation for the internal clock signal using the training pattern included in the clock-embedded data signal in the blank period. The training pattern in the blank period includes a first training clock signal modulated with a first modulation period during a first time, and includes a second training clock signal modulated with a second modulation period different from the first modulation period after the first time.