Abstract: Embodiments of the present disclosure include methods and apparatus for depositing a plurality of layers on a large area substrate. In one embodiment, a processing chamber for plasma deposition is provided. The processing chamber includes a showerhead and a substrate support assembly. The showerhead is coupled to an RF power source and a ground and includes a plurality of perforated gas diffusion members. A plurality of plasma applicators is disposed within the showerhead, wherein one plasma applicator of the plurality of plasma applicators corresponds to one of the plurality of perforated gas diffusion members. Further, a DC bias power source is coupled to a substrate support assembly.

Abstract: Disclosed herein is a device including a driving thin film transistor. The driving thin film transistor includes a metal oxide channel, a source electrode in contact with the driving metal oxide channel, and a top gate electrode disposed above the metal oxide channel and physically connected to the driving source electrode.

Abstract: Embodiments herein include thin-film transistors (TFTs) including channel layer stacks with layers having differing mobilities. The TFTs disclosed herein transport higher total current through both the low mobility and the high mobility channel layers due to higher carrier density in high mobility channel layer and/or the high mobility channel layers, which increases the speed of response of the TFTs. The TFTs further include a gate structure disposed over the channel layer stack. The gate structure includes one or more gate electrodes, and thus the TFTs are top-gate (TG), double-gate (DG), or bottom-gate (BG) TFTs. The channel layer stack includes a plurality of layers with differing mobilities. The layers with differing mobilities confer various benefits to the TFT. The high mobility layer increases the speed of response of the TFT.

Abstract: Embodiments of the present disclosure relate to flexible display devices, including dual-sided wet hardcoats for flexible cover lens structures, and related methods and coating systems. The flexible cover lens film has beneficial strength, elasticity. optical transmission, and anti-abrasion properties. In one or more embodiments. a cover lens structure for display devices includes a substrate layer including a first side and a second side. The cover lens structure includes a first wet hardcoat layer deposited on the first side of the substrate layer, and a second wet hardcoat layer deposited on the second side of the substrate layer. The cover lens structure includes one or more adhesion promotion layers formed above the second side. and a dry hardcoat layer formed above the second side.

Abstract: Techniques are disclosed for methods of post-treating an etch stop or a passivation layer in a thin film transistor to increase the stability behavior of the thin film transistor.

Abstract: Exemplary flexible coverlenses and the methods of making them are described. The methods may include exposing a surface of a substrate layer to a surface treatment plasma to form a treated surface of the substrate layer. A silicon-containing adhesion layer may be deposited on the treated surface of the substrate layer. A silane-containing adhesion promoter may be incorporated on the silicon-containing adhesion layer. The method may also include forming a hardcoat layer on the silicon-containing adhesion layer, where the silane-containing adhesion promoter is bonded to both the hardcoat layer and the silicon-containing adhesion layer. The exemplary flexible coverlenses made by the present methods are less susceptable to folding fatigue along a bending or folding axis of the coverlens.

Abstract: A method can include removing material from a first side of a diffuser block to form a back-side gradient surface of a diffuser, wherein the back-side gradient surface is a first concave surface, after removing the material from the first side, removing material from a second side of the diffuser block to form a front-side gradient surface of the diffuser, wherein the front-side gradient surface is a second concave surface, and forming a plurality of opening structures through the front-side gradient surface to the back-side gradient surface.

Abstract: Embodiments described herein relate to engineering metal oxide layer interfaces to improve electronic device stability. For example, a transistor device can include a base structure and a metal oxide layer disposed on the base structure. The metal oxide layer includes at least one region having a gradient profile with respect to oxygen (O2) composition.

Abstract: Sub-pixel circuits and methods of forming sub-pixel circuits that may be utilized in a display, such as an organic light-emitting diode (OLED) display, are provided. In one example, a sub-pixel includes a substrate, adjacent overhang structures, an anode, an OLED material, a cathode, an encapsulation layer stack. The encapsulation layer stack includes a first layer, a second layer disposed over the first layer, and a third layer. The first layer and the second layer have a first portion disposed over the cathode, a second portion disposed over a sidewall of each overhang structure, and a third portion disposed under an underside surface of an extension of each overhang structure. A gap is defined by contact of the first portion of the second layer and the third portion of the second layer. The third layer is disposed over the second layer outside of the gap.

Abstract: A method for registering an electronic device in one embodiment includes broadcasting access information of an electronic device to be registered, receiving a request for communication connection based on the broadcast access information of the electronic device from a user terminal, transmitting a request for confirmation of a device corresponding to the received request for communication connection to the user terminal, receiving device confirmation information from the user terminal as a result of manipulation of a user, generating device authentication information based on the confirmation information, receiving access point (AP) access information from the user terminal, performing communication connection with an electronic-device managing server based on the received AP access information while transmitting identification information of the electronic device, and requesting registration of the device in a user account stored in the electronic-device managing server based on the transmitted identificati

Abstract: Embodiments of the disclosure generally provide methods of forming a capacitor layer or a gate insulating layer with high dielectric constant as well as low film current leakage and desired film qualities for display applications. In one embodiment, a thin film transistor structure includes a dielectric layer formed on a substrate, wherein the dielectric layer is a zirconium containing material comprising aluminum, and gate, source and drain electrodes formed on the substrate, wherein the gate, source and drain electrodes formed above or below the dielectric layer.

Abstract: A diffuser includes a front-side gradient surface formed from a diffuser block, a back-side gradient surface formed from the diffuser block, and opening structures formed from the front-side gradient surface to the back-side gradient surface. Each opening structure includes a conical opening having a first end along the front-side gradient surface and a second end corresponding to an apex at a depth within the diffuser block, and a cylindrical opening formed from the depth to the back-side gradient surface. The opening structures are arranged in rows including a first set of rows and a second set of rows alternately positioned along a length of the diffuser block.

Abstract: Embodiments of the disclosure generally provide methods of forming a hybrid film stack that may be used as a capacitor layer or a gate insulating layer with a high dielectric constant as well as film qualities for display applications. In one embodiment, a thin film transistor structure include gate, source and drain electrodes formed on a substrate, and an insulating layer formed on a substrate, wherein the insulating layer is a hybrid film stack having a dielectric layer comprising a zirconium containing material disposed on an interface layer formed above or below the gate, source and drain electrodes.

Abstract: Embodiments of the present disclosure generally relate to nitrogen-rich silicon nitride and methods for depositing the same, and transistors and other devices containing the same. In one or more embodiments, a passivation film stack is provided and includes a silicon oxide layer disposed on a workpiece, a nitrogen-rich silicon nitride layer disposed on the silicon oxide layer, and a hydrogen-rich silicon nitride layer disposed on the nitrogen-rich silicon nitride layer. The hydrogen-rich silicon nitride layer has a greater hydrogen concentration than the nitrogen-rich silicon nitride layer.

Abstract: In one implementation, a method for cleaning a processing chamber is provided. The method comprises introducing a reactive species into a processing chamber having a residual high-k dielectric material formed on one or more interior surfaces of the processing chamber. The reactive species is formed from a halogen-containing gas mixture and the one or more interior surfaces include at least one surface having a coating material formed thereon. The method further comprises reacting the residual high-k dielectric material with the reactive species to form a volatile product. The method further comprises removing the volatile product from the processing chamber. The removal rate of the residual high-k dielectric material is greater than a removal rate of the coating material. The high-k dielectric material is selected from zirconium dioxide (ZrO2) and hafnium dioxide (HfO2). The coating material includes a compound selected from alumina (Al2O3), yttrium-containing compounds, and combinations thereof.

Abstract: Embodiments of the disclosure generally provide methods of forming a hybrid film stack that may be used as a capacitor layer or a gate insulating layer with a high dielectric constant as well as film qualities for display applications. In one embodiment, a thin film transistor structure include gate, source and drain electrodes formed on a substrate, and an insulating layer formed on a substrate, wherein the insulating layer is a hybrid film stack having a dielectric layer comprising a zirconium containing material disposed on an interface layer formed above or below the gate, source and drain electrodes.

Abstract: Embodiments described herein provide thin film transistors (TFTs) and processes to reduce plasma induced damage in TFTs. In one embodiment, a buffer layer is disposed over a substrate and a semiconductor layer is disposed over the buffer layer. A gate dielectric layer is disposed over the semiconductor layer. The gate dielectric layer contacts the semiconductor layer at an interface. The gate electrode 204 is disposed over the gate dielectric layer. The gate dielectric layer has a Dit of about 5e10 cm?2 eV?1 to about 5e11 cm?2 eV?1 and a hysteresis of about 0.10 V to about 0.30 V improve performance capability of the TFT while having a breakdown field between about 6 MV/cm and about 10 MV/cm.

Abstract: Disclosed herein is a device including a driving thin film transistor. The driving thin film transistor includes a metal oxide channel, a source electrode in contact with the driving metal oxide channel, and a top gate electrode disposed above the metal oxide channel and physically connected to the driving source electrode.

Abstract: Embodiments of the disclosure generally provide methods of forming a capacitor layer or a gate insulating layer with high dielectric constant as well as low film current leakage and desired film qualities for display applications. In one embodiment, a thin film transistor structure includes a dielectric layer formed on a substrate, wherein the dielectric layer is a zirconium containing material comprising aluminum, and gate, source and drain electrodes formed on the substrate, wherein the gate, source and drain electrodes formed above or below the dielectric layer.

Abstract: Embodiments of the present disclosure include methods and apparatus for depositing a plurality of layers on a large area substrate. In one embodiment, a processing chamber for plasma deposition is provided. The processing chamber includes a showerhead and a substrate support assembly. The showerhead is coupled to an RF power source and a ground and includes a plurality of perforated gas diffusion members. A plurality of plasma applicators is disposed within the showerhead, wherein one plasma applicator of the plurality of plasma applicators corresponds to one of the plurality of perforated gas diffusion members. Further, a DC bias power source is coupled to a substrate support assembly.