Patents by Inventor Sophia E. Weeks

Sophia E. Weeks has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • ADAPTIVE AND RETROSPECTIVE ENDPOINT DETECTION FOR AUTOMATED DELAYERING OF SEMICONDUCTOR SAMPLES
    Publication number: 20240094142
    Abstract: Adaptive endpoint detection is applied to delayering of a multi-layer sample utilizing a combination of dynamic and predetermined parameters. Retrospective evaluation of peaks and troughs can re-classify endpoints as signal properties emerge, enabling accurate mapping of endpoints to layers. The described techniques can be integrated with analysis operations and can be applied across a wide range of device types and manufacturing processes.
    Type: Application
    Filed: July 13, 2023
    Publication date: March 21, 2024
    Applicant: FEI Company
    Inventors: Sophia E. Weeks, Umesh Adiga
  • Adaptive endpoint detection for automated delayering of semiconductor samples
    Patent number: 11171048
    Abstract: Adaptive endpoint detection is applied to delayering of a multi-layer sample utilizing a combination of dynamic and predetermined parameters. Tuned predetermined parameters, varying between layers of the sample, allow automated operation across multiple sites of a device. A semiconductor logic device is described, having a zone of thick metal layers and a zone of thin metal layers. The described techniques can be integrated with analysis operations and can be applied across a wide range of device types and manufacturing processes.
    Type: Grant
    Filed: March 12, 2020
    Date of Patent: November 9, 2021
    Assignee: FEI Company
    Inventors: Sean O. Morgan-Jones, Sophia E. Weeks, Peter D. Carleson
  • ADAPTIVE ENDPOINT DETECTION FOR AUTOMATED DELAYERING OF SEMICONDUCTOR SAMPLES
    Publication number: 20210287938
    Abstract: Adaptive endpoint detection is applied to delayering of a multi-layer sample utilizing a combination of dynamic and predetermined parameters. Tuned predetermined parameters, varying between layers of the sample, allow automated operation across multiple sites of a device. A semiconductor logic device is described, having a zone of thick metal layers and a zone of thin metal layers. The described techniques can be integrated with analysis operations and can be applied across a wide range of device types and manufacturing processes.
    Type: Application
    Filed: March 12, 2020
    Publication date: September 16, 2021
    Applicant: FEI Company
    Inventors: Sean O. Morgan-Jones, Sophia E. Weeks, Peter D. Carleson