Patents by Inventor Sophia Mai-Simpson

Sophia Mai-Simpson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and apparatus for enhancing input/output error analysis in hardware sub-systems
    Patent number: 6934888
    Abstract: A method, apparatus, and computer instructions for processing errors in a hierarchical hardware sub-system in the data processing system in which the hierarchical hardware sub-system includes a host processor bridge having a mapping registers section and a control and status registers section. In response to detecting an error freezing the mapping registers section in the host bridge, a component within the hierarchical hardware sub-system connected to the host bridge is identified to form a selected component. An address is written to a register within the control and status registers section of the host bridge in which the address is to an error register in the component. Data is read in response to a result from the address written in the register being placed in the control and status registers portion of the host bridge.
    Type: Grant
    Filed: March 7, 2002
    Date of Patent: August 23, 2005
    Assignee: International Business Machines Corporation
    Inventors: Gordon D. McIntosh, Sophia Mai-Simpson
  • Method and apparatus for enhancing input/output error analysis in hardware sub-systems
    Publication number: 20030172323
    Abstract: A method, apparatus, and computer instructions for processing errors in a hierarchical hardware sub-system in the data processing system in which the hierarchical hardware sub-system includes a host processor bridge having a mapping registers section and a control and status registers section. In response to detecting an error freezing the mapping registers section in the host bridge, a component within the hierarchical hardware sub-system connected to the host bridge is identified to form a selected component. An address is written to a register within the control and status registers section of the host bridge in which the address is to an error register in the component. Data is read in response to a result from the address written in the register being placed in the control and status registers portion of the host bridge.
    Type: Application
    Filed: March 7, 2002
    Publication date: September 11, 2003
    Applicant: International Business Machines Corporation
    Inventors: Gordon D. McIntosh, Sophia Mai-Simpson