Patents by Inventor Sophie BERNASCONI

Sophie BERNASCONI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method for securing an integrated circuit upon making it
    Patent number: 11276652
    Abstract: A method for securing an integrated circuit upon making it includes the steps of delimiting said integrated circuit into a first so-called standard zone and into a second so-called security zone, and randomly misaligning in said security zone between a lower level of interconnection holes and an upper level of interconnection holes generating the formation of an interconnection structure having a random distribution of electrical contact and non-contact points. Also described is a secured integrated circuit obtainable using such a method.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: March 15, 2022
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Christelle Charpin-Nicolle, Sophie Bernasconi, Aomar Halimaoui, Florian Pebay-Peyroula
  • METHOD FOR SECURING AN INTEGRATED CIRCUIT UPON MAKING IT
    Publication number: 20200279816
    Abstract: A method for securing an integrated circuit upon making it includes the of delimiting said integrated circuit into a first so-called standard zone and into a second so-called security zone, and randomly misaligning in said security zone between a lower level of interconnection holes and an upper level of interconnection holes generating the formation of an interconnection structure having a random distribution of electrical contact and non-contact points. Also described is a secured integrated circuit obtainable using such a method.
    Type: Application
    Filed: December 23, 2019
    Publication date: September 3, 2020
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Christelle Charpin-Nicolle, Sophie Bernasconi, Aomar Halimaoui, Florian Pebay-Peyroula
  • Method of manufacturing a memory device
    Patent number: 10651376
    Abstract: The present invention relates to a memory device comprising a first electrode (27), a second electrode (28) and an active portion that can change conductive state, positioned between a first face of the first electrode (27) and a first face of the second electrode (28). The first electrode (27) comprises an upper portion forming the first face of the first electrode (27). At least one out of the upper portion and the active portion that can change conductive state comprises a porous layer (15).
    Type: Grant
    Filed: January 23, 2018
    Date of Patent: May 12, 2020
    Assignees: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, STMICROELECTRONICS (CROLLES 2) SAS
    Inventors: Sophie Bernasconi, Christelle Charpin-Nicolle, Aomar Halimaoui
  • Method for producing a resistive memory cell
    Patent number: 10411072
    Abstract: A method for manufacturing a memory cell includes forming a stack of layers comprising a first electrode and a dielectric layer, and forming a second electrode. Forming the second electrode includes depositing the second electrode on the dielectric layer, and defining the contour of the second electrode in such a way that the second electrode forms a protruding element above the dielectric layer having inclined flanks, the angle between the flanks of the second electrode forming an acute angle with the plane wherein the dielectric layer mainly extends.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: September 10, 2019
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Sophie Bernasconi, Christelle Charpin-Nicolle, Anthony De Luca
  • METHOD OF MANUFACTURING A MEMORY DEVICE
    Publication number: 20180254414
    Abstract: The present invention relates to a memory device comprising a first electrode (27), a second electrode (28) and an active portion that can change conductive state, positioned between a first face of the first electrode (27) and a first face of the second electrode (28). The first electrode (27) comprises an upper portion forming the first face of the first electrode (27). At least one out of the upper portion and the active portion that can change conductive state comprises a porous layer (15).
    Type: Application
    Filed: January 23, 2018
    Publication date: September 6, 2018
    Applicants: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, STMICROELECTRONICS (CROLLES 2) SAS
    Inventors: Sophie BERNASCONI, Christelle Charpin-Nicolle, Aomar Halimaoui
  • METHOD FOR PRODUCING A RESISTIVE MEMORY CELL
    Publication number: 20170162627
    Abstract: A method for manufacturing a memory cell includes forming a stack of layers comprising a first electrode and a dielectric layer, and forming a second electrode. Forming the second electrode includes depositing the second electrode on the dielectric layer, and defining the contour of the second electrode in such a way that the second electrode forms a protruding element above the dielectric layer having inclined flanks, the angle between the flanks of the second electrode forming an acute angle with the plane wherein the dielectric layer mainly extends.
    Type: Application
    Filed: September 30, 2016
    Publication date: June 8, 2017
    Applicant: Commissariat A L'Energie Atomique et aux Energies Alternatives
    Inventors: Sophie BERNASCONI, Christelle CHARPIN-NICOLLE, Anthony DE LUCA