Abstract: Systems and methods for implementing a zero overhead loop in a microprocessor or microprocessor based system/chip are disclosed. The systems and methods include the use of a breakpoint mechanism which is additionally used in debugging in order to provide some of the looping functionality.

Abstract: A system and method for implementing a zero overhead loop in a microprocessor or microprocessor based system/chip.

Abstract: A “virtual on-chip memory” that provides advantages as compared to an on-chip memory that utilizes a cache. In accordance with the invention, when a CPU attempts to access a memory address that is not on-chip, the access is aborted and the abort is handled at a page level. A single page table is utilized in which each entry constitutes an address in the virtual address space that will be mapped to a page of on-chip memory. The CPU obtains the missing data, updates the page table, and continues execution from the aborted point. Because aborts are handled at the page level rather than the line level, the virtual on-chip memory is less expensive to implement than a cache. Furthermore, critical real-time applications can be stored within a non-virtual portion of the memory space to ensure that they are not stalled.

Abstract: A system and method for accelerated processing of streams of dependent instructions, such as those encountered in the G.726 codec, in a microprocessor or microprocessor-based system/chip. In a preferred implementation, a small RISC-like special purpose processor is implemented within a larger general purpose processor for handling the streams of dependent instructions.