Abstract: The present invention relates to a memory cell with a memory capacitor (110) on an active semiconductor region (104), the memory capacitor having a first capacitor-electrode layer, which, in a cross-sectional view of the memory cell, has first (218.1) and second (218.2) electrode-layer sections that extend on the active semiconductor region in parallel to the surface of the active semiconductor region at a vertical distance to each other and that are electrically connected by a third electrode-layer section extending vertically, that is, perpendicular to the surface of the active semiconductor region. A control transistor (112) is connected with a conductive second capacitor electrode layer that extends between the first and second electrode-layer sections and is electrically isolated from them by an isolation layer (116). Achieved advantages comprise a high manufacturing yield can, reduced fabrication cost and reduced risk of junction leakage by a small area required for the memory cell.