Abstract: A method is provided for self-aligned multi-patterning on a semiconductor workpiece using an integrated sequence of processing steps executed on a common manufacturing platform hosting one or more film-forming modules, one or more etching modules, and one or more transfer modules. A workpiece having a mandrel pattern formed thereon is received into the common manufacturing platform. A sidewall spacer pattern is formed based, at least in part, on the mandrel pattern, the sidewall spacer pattern having a plurality of second features separated by a second pitch distance with the first pitch distance being greater than the second pitch distance. The integrated sequence of processing steps is executed within the common manufacturing platform without leaving the controlled environment and the transfer modules are used to transfer the workpiece between the processing modules while maintaining the workpiece within the controlled environment. Broadly, forming a sidewall spacer pattern based on the mandrel pattern.

Abstract: An exemplary method of forming a semiconductor device includes forming, in a substrate, an active region protruding vertically from a major surface of the substrate, the active region including a semiconductor source-drain (S/D) region and a first 3-D channel structure, the S/D region physically contacting the first 3-D channel structure, and forming an opening extending into the S/D region, the opening having a depth greater than half of a height of the first 3-D channel structure; and forming a metallic plug in the opening, the metallic plug making electrical contact with the S/D region.

Abstract: Embodiments of methods and systems for patterning of low aspect ratio stacks are described. In one embodiment, a method may include receiving a substrate comprising a patterned organic planarizing layer (OPL) mask wherein a surface of the OPL mask is exposed, the OPL mask landing on a dielectric layer. The method may also include performing a partial etch of the dielectric layer in a region exposed by the OPL mask. Additionally, the method may include depositing a capping material on a surface of the OPL mask. The method may also include performing a cyclical process of the partial etch of the dielectric layer and deposition of the capping material on a surface of the OPL mask until the dielectric layer is removed to a target depth. In such embodiments, the cyclical process generates an output patterned substrate with a target line edge roughness (LER).

Abstract: A method is provided for self-aligned multi-patterning on a semiconductor workpiece using an integrated sequence of processing steps executed on a common manufacturing platform hosting film-forming modules, etching modules, and transfer modules. A workpiece having a mandrel pattern formed thereon is received into the common manufacturing platform. A sidewall spacer pattern is formed based, at least in part, on the mandrel pattern, the sidewall spacer pattern having a plurality of second features separated by a second pitch distance with the first pitch distance being greater than the second pitch distance. The integrated sequence of processing steps is executed within the common manufacturing platform without leaving the controlled environment and the transfer modules are used to transfer the workpiece between the processing modules while maintaining the workpiece within the controlled environment.

Abstract: Embodiments of methods and systems for patterning of low aspect ratio stacks are described. In one embodiment, a method may include receiving a substrate comprising a patterned organic planarizing layer (OPL) mask wherein a surface of the OPL mask is exposed, the OPL mask landing on a dielectric layer. The method may also include performing a partial etch of the dielectric layer in a region exposed by the OPL mask. Additionally, the method may include depositing a capping material on a surface of the OPL mask. The method may also include performing a cyclical process of the partial etch of the dielectric layer and deposition of the capping material on a surface of the OPL mask until the dielectric layer is removed to a target depth. In such embodiments, the cyclical process generates an output patterned substrate with a target line edge roughness (LER).

Abstract: A method is provided for self-aligned multi-patterning on a semiconductor workpiece using an integrated sequence of processing steps executed on a common manufacturing platform hosting one or more film-forming modules, one or more etching modules, and one or more transfer modules. A workpiece having a mandrel pattern formed thereon is received into the common manufacturing platform. A sidewall spacer pattern is formed based, at least in part, on the mandrel pattern, the sidewall spacer pattern having a plurality of second features separated by a second pitch distance with the first pitch distance being greater than the second pitch distance. The integrated sequence of processing steps is executed within the common manufacturing platform without leaving the controlled environment and the transfer modules are used to transfer the workpiece between the processing modules while maintaining the workpiece within the controlled environment. Broadly, forming a sidewall spacer pattern based on the mandrel pattern.

Abstract: A method is provided for self-aligned multi-patterning on a semiconductor workpiece using an integrated sequence of processing steps executed on a common manufacturing platform hosting film-forming modules, etching modules, and transfer modules. A workpiece having a mandrel pattern formed thereon is received into the common manufacturing platform. A sidewall spacer pattern is formed based, at least in part, on the mandrel pattern, the sidewall spacer pattern having a plurality of second features separated by a second pitch distance with the first pitch distance being greater than the second pitch distance. The integrated sequence of processing steps is executed within the common manufacturing platform without leaving the controlled environment and the transfer modules are used to transfer the workpiece between the processing modules while maintaining the workpiece within the controlled environment.

Abstract: Provided is a method of patterning spacers, the method comprising: providing an initial patterned structure in a substrate in a processing chamber, the initial patterned structure comprising an organic mandrel and an underlying layer; exposing the patterned structure in a direct current superposition (DCS) plasma treatment process, the process depositing a layer of a first material on the initial patterned structure; performing an atomic layer conformal deposition process using a second material, the first material providing protection to the organic mandrel at the beginning of the atomic layer conformal deposition process; performing a spacer etch mandrel pull process, the process creating a final patterned structure with a target final sidewall angle; concurrently controlling integration operating variables in the DCS plasma treatment process, the atomic layer conformal deposition process, and the spacer etch mandrel pull process in order to meet the target final sidewall angle and other integration objecti

Abstract: A method to implement self-aligned triple patterning techniques for the processing of substrates is provided. In one embodiment, a self-aligned triple processing technique utilizing an organic spacer is provided. The organic spacer may be formed utilizing any of a wide range of techniques including, but not limited to, plasma deposition and spin on deposition. In one embodiment, the organic spacer may be formed via a cyclic deposition etch process. In one embodiment, the self-aligned triple patterning technique may be utilized to form patterned structures on a substrate at pitches of 26 nm or less.

Abstract: Provide is a method of patterning spacers, the method comprising: providing an initial patterned structure in a substrate in a processing chamber, the initial patterned structure comprising an organic mandrel and an underlying layer; exposing the patterned structure in a direct current superposition (DCS) plasma treatment process, the process depositing a layer of a first material on the initial patterned structure; performing an atomic layer conformal deposition process using a second material, the first material providing protection to the organic mandrel at the beginning of the atomic layer conformal deposition process; performing a post spacer etch mandrel pull process, the process creating a final patterned structure with a target final sidewall angle; concurrently controlling integration operating variables in the exposing the patterned structure, the atomic layer conformal deposition process, and the post spacer etch mandrel pull process in order to meet the target final sidewall angle and other integr