Patents by Inventor Sorav Bansal

Sorav Bansal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11442712
    Abstract: A method, apparatus and system required to realize an optimization opportunity are disclosed. If an expression involves unsequenced evaluations involving side-effects and optionally references, then the expression is translated into optimized code that may involve optimized register usage, or optimized use of the underlying vectorization hardware. An alias-analysis logic is able to identify must-not-alias relationships through such expression tree structures. These must-not-alias relationships are helpful not just in optimizing the performance of that particular expression (from which these must-not-alias relationships were derived) but also in the performance of any other surrounding program statements that access the state elements participating in these must-not-alias relationships.
    Type: Grant
    Filed: June 10, 2021
    Date of Patent: September 13, 2022
    Assignee: INDIAN INSTITUTE OF TECHNOLOGY DELHI
    Inventors: Sorav Bansal, Ankush Phulia, Vaibhav Bhagee
  • Publication number: 20210389935
    Abstract: The present subject matter refers the method, apparatus and the system required to realize an optimization opportunity. If an expression involves unsequenced evaluations involving side-effects and optionally references, then the method is able to translate this into optimized code that may involve optimized register usage, or optimized use of the underlying vectorization hardware. The system includes an alias-analysis logic that is able to identify must-not-alias relationships through such expression tree structures. These must-not-alias relationships are helpful not just in optimizing the performance of that particular expression (from which these must-not-alias relationships were derived) but also the performance of any other surrounding program statements that access the state elements participating in these must-not-alias relationships.
    Type: Application
    Filed: June 10, 2021
    Publication date: December 16, 2021
    Inventors: Sorav Bansal, Ankush Phulia, Vaibhav Bhagee
  • Patent number: 7831796
    Abstract: A method is disclosed for dynamically allocating main memory among applications. The method includes maintaining a first list and a second list, each list having a plurality of pages, maintaining a cache memory module having a selected size, and resizing the selected size by adaptively selecting the first or second list and adding pages to the selected list to increase the selected size and subtracting pages from the selected list to decrease the selected size.
    Type: Grant
    Filed: November 5, 2008
    Date of Patent: November 9, 2010
    Assignee: International Business Machines Corporation
    Inventors: Sorav Bansal, Paul Edward McKenney, Dharmendra Shantilal Modha
  • Patent number: 7712092
    Abstract: An efficient binary translator uses peephole translation rules to directly translate executable code from one instruction set to another. In a preferred embodiment, the translation rules are generated using superoptimization techniques that enable the translator to automatically learn translation rules for translating code from the source to target instruction set architecture.
    Type: Grant
    Filed: February 12, 2008
    Date of Patent: May 4, 2010
    Assignee: The Board of Trustees of the Leland Stanford Junior University
    Inventors: Sorav Bansal, Alex Aiken
  • Publication number: 20090055617
    Abstract: A method is disclosed for dynamically allocating main memory among applications. The method includes maintaining a first list and a second list, each list having a plurality of pages, maintaining a cache memory module having a selected size, and resizing the selected size by adaptively selecting the first or second list and adding pages to the selected list to increase the selected size and subtracting pages from the selected list to decrease the selected size.
    Type: Application
    Filed: November 5, 2008
    Publication date: February 26, 2009
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Sorav Bansal, Paul Edward McKenney, Dharmendra Shantilal Modha
  • Patent number: 7487320
    Abstract: An apparatus and system are disclosed for dynamically allocating main memory among applications. The apparatus includes a cache memory module configured to maintain a first list and a second list, each list having a plurality of pages, and a resize module configured to resize the cache by adaptively selecting the first or second list and subtracting pages from or adding pages to the selected list. The system includes the apparatus and a cache replacement module configured to adaptively distribute a workload between the first list and the second list.
    Type: Grant
    Filed: December 15, 2004
    Date of Patent: February 3, 2009
    Assignee: International Business Machines Corporation
    Inventors: Sorav Bansal, Paul Edward McKenney, Dharmendra Shantilal Modha
  • Publication number: 20060129782
    Abstract: An apparatus, system, and method are disclosed for dynamically allocating main memory among applications. The apparatus includes a cache memory module configured to maintain a first list and a second list, each list having a plurality of pages, and a resize module configured to resize the cache by adaptively selecting the first or second list and subtracting pages from or adding pages to the selected list. The system includes the apparatus and a cache replacement module configured to adaptively distribute a workload between the first list and the second list. The method includes maintaining a first list and a second list, each list having a plurality of pages, maintaining a cache memory module having a selected size, and resizing the selected size by adaptively selecting the first or second list and adding pages to the selected list to increase the selected size and subtracting pages from the selected list to decrease the selected size.
    Type: Application
    Filed: December 15, 2004
    Publication date: June 15, 2006
    Inventors: Sorav Bansal, Paul McKenney, Dharmendra Modha
  • Publication number: 20060069876
    Abstract: A method and system of managing data retrieval in a computer comprising a cache memory and auxiliary memory comprises organizing pages in the cache memory into a first and second clock list, wherein the first clock list comprises pages with short-term utility and the second clock list comprises pages with long-term utility; requesting retrieval of a particular page in the computer; identifying requested pages located in the cache memory as a cache hit; transferring requested pages located in the auxiliary memory to the first clock list; relocating the transferred requested pages into the second clock list upon achieving at least two consecutive cache hits of the transferred requested page; logging a history of pages evicted from the cache memory; and adaptively varying a proportion of pages marked as short and long-term utility to increase a cache hit ratio of the cache memory by utilizing the logged history of evicted pages.
    Type: Application
    Filed: September 30, 2004
    Publication date: March 30, 2006
    Inventors: Sorav Bansal, Dharmendra Modha