Patents by Inventor Soraya Ghiasi

Soraya Ghiasi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080300817
    Abstract: A system for identifying a subset of sensors to sample to reduce the frequency of sensor access. The system determines rise times and records values for the sensors in the system. A time criticality of the sensors is determined based on the rise times. The system processes the sensors by first creating sensor subsets based on one or more constraints on the sensors. The system monitors the values of the sensors in a sensor subset and flags a sensor when it makes a determination that, prior to a next scheduled sampling of the sensor subset, the value of a sensor in the monitored sensor subset will exceed a threshold constraint. The system moves those flagged sensors to a second sensor subset which complies with the sensor's constraints.
    Type: Application
    Filed: May 29, 2007
    Publication date: December 4, 2008
    Inventors: Andreas Bieswanger, Michael S. Floyd, Andrew J. Geissler, Soraya Ghiasi, Hye-Young McCreary, Guillermo J. Silva, Malcolm S. Ware
  • Publication number: 20080209243
    Abstract: A power management system schedules the voltage and frequency of processors in a data processing system based on two criteria. The first criterion is a prediction of the performance that the work currently running on the processor will experience at the different frequencies that are available. The second criterion is a system-wide constraint on the total power budget allocated to processors. Based on these criteria, low-level code sets the frequency and voltage of the processors in the system to match what the operating system is currently running on them.
    Type: Application
    Filed: April 17, 2008
    Publication date: August 28, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Soraya Ghiasi, Thomas Walter Keller, Ramakrishna Kotla, Freeman Leigh Rawson
  • Publication number: 20080184256
    Abstract: A data processing system includes a power supply, a plurality of processors wherein each processor is separately powerable by the power supply under operating system control. The operating system determines periodically a measure of system utilization and controls the switches to alter the number of active (powered) processors where the number of active processors reflects the measured system utilization and a set of utilization threshold values. System utilization may be based on the number of active tasks. The utilization thresholds preferably include a maximum threshold and a minimum threshold. A measured utilization exceeding the maximum threshold causes an increase in the number of active processors while utilization less than the minimum threshold causes a decrease in the number of active processors. The utilization thresholds may be determined from threshold factors that reflect time and date information, quality of service information, or a weighted average of historical utilization values.
    Type: Application
    Filed: March 31, 2008
    Publication date: July 31, 2008
    Inventors: Wesley Michael Felter, Soraya Ghiasi
  • Patent number: 7386739
    Abstract: A power management system schedules the voltage and frequency of processors in a data processing system based on two criteria. The first criterion is a prediction of the performance that the work currently running on the processor will experience at the different frequencies that are available. The second criterion is a system-wide constraint on the total power budget allocated to processors. Based on these criteria, low-level code sets the frequency and voltage of the processors in the system to match what the operating system is currently running on them.
    Type: Grant
    Filed: May 3, 2005
    Date of Patent: June 10, 2008
    Assignee: International Business Machines Corporation
    Inventors: Soraya Ghiasi, Thomas Walter Keller, Jr., Ramakrishna Kotla, Freeman Leigh Rawson, III
  • Publication number: 20080133180
    Abstract: A weighted event counting system and method for processor performance measurements provides low latency and low error performance measurement capability. A weighted performance counter accumulates a performance count according to a plurality of event signals provided from functional units in the processor. Differing weights are applied to the event signals in according to the correlation between each event with processor performance. The weights may be provided from programmable registers, so that the weights can be adjusted under program control. The event signals may be combined to reduce the bit-width of the set of event signal, with mutually-exclusive events merged in single fields of the combinatorial result and events having the same weights merged according to a sub-total. The weights are applied to the combinatorial result and used to update a performance count. The performance count can then be used by power management software or hardware to make adjustments in operating parameters of the processor.
    Type: Application
    Filed: December 5, 2007
    Publication date: June 5, 2008
    Inventors: Michael S. Floyd, Soraya Ghiasi, Thomas W. Keller, Karthick Rajamani, Freeman Leigh Rawson, Juan C. Rubio
  • Publication number: 20080082844
    Abstract: A method and system for improving processing performance by using activity factor headroom provides improved performance while meeting power management constraints in a processing system. The method and system estimate the power consumption of the system from a model that relates measured activities at a present operating point to power consumption for any available operating point of one or more processors in the system. The method then chooses the operating point(s) with the highest performance among the available operating points that will still meet budgetary constraints or specific thresholds of power consumption. The budgetary constraints or specific thresholds may be dynamically adjusted, and the method will update the operating point(s) to maintain safe operation and maximize performance. The method provides the best performance for the executing workload while ensuring safe operation.
    Type: Application
    Filed: October 3, 2006
    Publication date: April 3, 2008
    Inventors: Soraya Ghiasi, Thomas Walter Keller, Karthick Rajamani, Freeman Leigh Rawson, Juan C. Rubio
  • Patent number: 7340378
    Abstract: A weighted event counting system and method for processor performance measurements provides low latency and low error performance measurement capability. A weighted performance counter accumulates a performance count according to a plurality of event signals provided from functional units in the processor. Differing weights are applied to the event signals in according to the correlation between each event with processor performance. The weights may be provided from programmable registers, so that the weights can be adjusted under program control. The event signals may be combined to reduce the bit-width of the set of event signal, with mutually-exclusive events merged in single fields of the combinatorial result and events having the same weights merged according to a sub-total. The weights are applied to the combinatorial result and used to update a performance count. The performance count can then be used by power management software or hardware to make adjustments in operating parameters of the processor.
    Type: Grant
    Filed: November 30, 2006
    Date of Patent: March 4, 2008
    Assignee: International Business Machines Corporation
    Inventors: Michael S. Floyd, Soraya Ghiasi, Thomas W. Keller, Jr., Karthick Rajamani, Freeman Leigh Rawson, III, Juan C. Rubio
  • Publication number: 20060253715
    Abstract: A power management system schedules the voltage and frequency of processors in a data processing system based on two criteria. The first criterion is a prediction of the performance that the work currently running on the processor will experience at the different frequencies that are available. The second criterion is a system-wide constraint on the total power budget allocated to processors. Based on these criteria, low-level code sets the frequency and voltage of the processors in the system to match what the operating system is currently running on them.
    Type: Application
    Filed: May 3, 2005
    Publication date: November 9, 2006
    Applicant: International Business Machines Corporation
    Inventors: Soraya Ghiasi, Thomas Keller, Ramakrishna Kotla, Freeman Rawson
  • Publication number: 20060168571
    Abstract: A method, computer program product, and a data processing system for optimizing task throughput in a multi-processor system. A performance metric is calculated based on performance counters measuring characteristics of a task executed at one of a plurality of processor frequencies available in the multi-processor system. The characteristics measured by the performance counters indicate activity in the processor as well as memory activity. A performance metric provides a means using measured data at one available frequency to predict performance at another processor frequency available in the multi-processing system. Performance loss minimization is used to assign a particular task to a particular frequency. Additionally, the present invention provides a mechanism for priority load balancing of tasks in a manner that minimizes cumulative performance loss incurred by execution of all tasks in the system.
    Type: Application
    Filed: January 27, 2005
    Publication date: July 27, 2006
    Applicant: International Business Machines Corporation
    Inventors: Soraya Ghiasi, Thomas Keller, Ramakrishna Kotla, Freeman Rawson
  • Publication number: 20060123422
    Abstract: A data processing system includes a power supply, a plurality of processors wherein each processor is separately powerable by the power supply under operating system control. The operating system determines periodically a measure of system utilization and controls the switches to alter the number of active (powered) processors where the number of active processors reflects the measured system utilization and a set of utilization threshold values. System utilization may be based on the number of active tasks. The utilization thresholds preferably include a maximum threshold and a minimum threshold. A measured utilization exceeding the maximum threshold causes an increase in the number of active processors while utilization less than the minimum threshold causes a decrease in the number of active processors. The utilization thresholds may be determined from threshold factors that reflect time and date information, quality of service information, or a weighted average of historical utilization values.
    Type: Application
    Filed: December 2, 2004
    Publication date: June 8, 2006
    Applicant: International Business Machines Corporation
    Inventors: Wesley Felter, Soraya Ghiasi