Abstract: Packets are received via a plurality of ports, and packets are switched between the plurality of ports. Packets received via the plurality of ports are stored in a memory, and buffers are allocated in the memory for storing packets. An aging mechanism to indicate allocated buffers that are to be deallocated is implemented, and buffers that are indicated to be deallocated by the aging mechanism are deallocated.

Abstract: Systems and apparatus for managing buffers in a buffer memory are described. In at least one aspect, a system includes a buffer memory including a plurality of buffers; an allocation memory including a plurality of allocation data elements associated with the plurality of buffers; an allocation clear register coupled with the allocation memory; a reclaim memory including a plurality of reclaim data elements each associated with an allocation data element and corresponding buffer; a reclaim clear register coupled with the reclaim memory; an allocation register configured to receive one or more allocation data elements from the allocation memory; and a buffer manager.

Abstract: A network switch may include a buffer management module to manage buffers in a buffer memory. The buffer management module may include an Allocation SRAM and a Reclaim SRAM. Each buffer in the buffer memory may be associated with a corresponding bit in the Allocation SRAM and Reclaim SRAM. A line including bits indicating available buffers in the Allocation SRAM may be written to the allocation register, and the buffer management module may allocate buffers from the allocation register. A reclaim module may age bits in the Reclaim SRAM. The reclaim module may reclaim buffers by searching corresponding lines in the Allocation SRAM and Reclaim SRAM and comparing the values of bits in the two lines.

Abstract: The present invention provides a method and apparatus for finding the next free bit in a register, starting from a known pointer. The present invention breaks the N bits of a vector in a register into M parts, performs an AND operation to all bits of each part respectively, and uses the operation result for each part as a bit to generate a check sector. It is then decided whether the register has a free bit by performing an AND operation to all bits of the check sector. If the result is 1, the register is full. Otherwise, the next free bit is found by looking for a forward free bit from the pointed-to bit until the end of the pointed-to part; a forward available part, having a free bit, from the pointed-to part until the end of the register; and an available part, having a free bit, from the beginning of the register. The present invention also searches the parts to locate the free bit therein.

Abstract: An integrated circuit comprises n storage elements, arranged to form a scan chain, that define m clock domains, wherein m?2 and n?m. A clock driver is adapted to provide m domain clock signals and m switching units, each adapted to provide one of the m domain clock signals to the storage elements in a respective one of the m clock domains in response to a first state of a scan mode signal, and to provide a single scan clock signal to the n storage elements in the m clock domains in response to a second state of the scan mode signal. The n storage elements are adapted to interconnect in series in response to a scan shift signal and to serially shift bits through the scan chain in response to the scan clock signal when the scan to mode signal is in the second state.