Abstract: Various example implementations are directed to circuits and methods for communicating between disparate processor circuits. According to an example implementation, a circuit arrangement includes a plurality of processor circuits and an inter-processor communication circuit. The inter-processor communication circuit is configured to provide, for each pair of the processor circuits, a respective communication channel between the pair of processor circuits. The inter-processor communication circuit includes a plurality of buffers including a respective first buffer and a respective second buffer for each communication channel. An access control circuit included in the inter-processor communication circuit is configured to restrict write access to the respective first buffer to the first processor circuit and restrict write access to the respective second buffer to the second processor circuit.

Abstract: An apparatus is disclosed that includes a processing sub-system having a plurality of processor circuits and an interrupt control circuit. The interrupt control circuit is configured to, in response to a peripheral interrupt, initiate performance of a task indicated by the peripheral interrupt by at least one of the plurality of processor circuits. The processing sub-system is configured to generate a power-down control signal in response to suspension of the plurality of processor circuits. A power management circuit disables power to the processing sub-system, including the interrupt control circuit, in response to the power-down control signal. The power management circuit enables power to the processing sub-system in response to a power-up control signal. The apparatus also includes a proxy interrupt control circuit configured to generate the power-up control signal in response to receiving a peripheral interrupt and power to the processing sub-system being disabled.

Abstract: Various example implementations are directed to circuits and methods for communicating between disparate processor circuits. According to an example implementation, a circuit arrangement includes a plurality of processor circuits and an inter-processor communication circuit. The inter-processor communication circuit is configured to provide, for each pair of the processor circuits, a respective communication channel between the pair of processor circuits. The inter-processor communication circuit includes a plurality of buffers including a respective first buffer and a respective second buffer for each communication channel. An access control circuit included in the inter-processor communication circuit is configured to restrict write access to the respective first buffer to the first processor circuit and restrict write access to the respective second buffer to the second processor circuit.

Abstract: An apparatus is disclosed that includes a processing sub-system having a plurality of processor circuits and an interrupt control circuit. The interrupt control circuit is configured to, in response to a peripheral interrupt, initiate performance of a task indicated by the peripheral interrupt by at least one of the plurality of processor circuits. The processing sub-system is configured to generate a power-down control signal in response to suspension of the plurality of processor circuits. A power management circuit disables power to the processing sub-system, including the interrupt control circuit, in response to the power-down control signal. The power management circuit enables power to the processing sub-system in response to a power-up control signal. The apparatus also includes a proxy interrupt control circuit configured to generate the power-up control signal in response to receiving a peripheral interrupt and power to the processing sub-system being disabled.