Abstract: In a power control system a server maintains asset models that represent asset behaviour, each asset model being in real-time communication with its asset to dynamically inform the model of the status of the asset. A test is performed at the server by issuing a command to an asset requesting the asset to perform a function. Sensors at the asset measure physical parameters at the asset and report these to the server. The server determines whether the asset responded to the command and, if the asset responded, how it responded over time. The server establishes a model for the asset in terms of an energy capacitance and a time constant based on the measured response. An optimizer determines which assets are to participate in which service models. The server sends instructions to the selected assets to attempt to fulfill the services.

Abstract: In a power control system a server maintains asset models that represent asset behaviour, each asset model being in real-time communication with its asset to dynamically inform the model of the status of the asset. A test is performed at the server by issuing a command to an asset requesting the asset to perform a function. Sensors at the asset measure physical parameters at the asset and report these to the server. The server determines whether the asset responded to the command and, if the asset responded, how it responded over time. The server establishes a model for the asset in terms of an energy capacitance and a time constant based on the measured response. An optimizer determines which assets are to participate in which service models. The server sends instructions to the selected assets to attempt to fulfill the services.

Abstract: The present invention relates to a method of manufacturing an array chip, comprising the steps of: i) depositing at least one ligand onto the active surface of a wafer substrate, having at least one scribe line, the active surface being the reverse of the surface comprising the at least one scribe line; ii) detecting the ligand in relation to the at least one scribe line; and iii) breaking the wafer substrate along the at least one scribe line, to produce at least one array chip.