Patents by Inventor Sorin Cristoloveanu
Sorin Cristoloveanu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10062681Abstract: A protection device for protecting an IC against electrostatic discharge includes a buried insulant layer having a thickness that is no greater than fifty nanometers with bipolar transistors arranged thereon, one of which is NPN and the other of which is PNP. A base of one merges with a collector of the other. The transistors selectively conduct a discharge current between electrodes. A first semiconductor ground plane under the buried insulant layer is capable of being electrically biased and extends underneath the base of the first bipolar transistor. The ground plane and a base of one transistor have the same doping. However, its dopant density is at least tenfold greater than that of the base.Type: GrantFiled: May 10, 2017Date of Patent: August 28, 2018Assignees: Commissariat à l'énergie atomique et aux énergies alternatives, STMicroelectronics SA, Centre National de la Recherche ScientifiqueInventors: Yohann Solaro, Sorin Cristoloveanu, Claire Fenouillet-Beranger, Pascal Fonteneau
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Publication number: 20170256531Abstract: A protection device for protecting an IC against electrostatic discharge includes a buried insulant layer having a thickness that is no greater than fifty nanometers with bipolar transistors arranged thereon, one of which is NPN and the other of which is PNP. A base of one merges with a collector of the other. The transistors selectively conduct a discharge current between electrodes. A first semiconductor ground plane under the buried insulant layer is capable of being electrically biased and extends underneath the base of the first bipolar transistor. The ground plane and a base of one transistor have the same doping. However, its dopant density is at least tenfold greater than that of the base.Type: ApplicationFiled: May 10, 2017Publication date: September 7, 2017Inventors: Yohann Solaro, Sorin Cristoloveanu, Claire Fenouillet-Beranger, Pascal Fonteneau
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Patent number: 9666577Abstract: The invention relates to an IC with an electrostatic discharge protection device. There is a buried insulant layer 50 nm or less in thickness and first and second bipolar transistors on the insulant layer, one being an npn transistor and the other a pnp transistor. The base of the first transistor is merged with the collector of the second transistor and the base of the second transistor is merged with the collector of the first transistor. The first and second bipolar transistors are configured to selectively conduct a discharge current between two electrodes of the protection device. There is a first semiconductor ground plane under the insulant layer, being electrically biased, extending until it is plumb with the base of the first bipolar transistor, exhibiting a first type of doping identical to that of the base of the first bipolar transistor with a doping density at least ten times greater.Type: GrantFiled: August 4, 2014Date of Patent: May 30, 2017Assignees: Commissariat à l'énergie atomique et aux énergies alternatives, STMicroelectronics SA, Centre National De La Recherche ScientifiqueInventors: Yohann Solaro, Sorin Cristoloveanu, Claire Fenouillet-Beranger, Pascal Fonteneau
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Patent number: 9276102Abstract: A tunnel-effect transistor the drain region of which includes a first zone doped with a doping of a first type, and a second zone doped with a doping of a second type forming a junction with the first zone.Type: GrantFiled: July 8, 2013Date of Patent: March 1, 2016Assignees: Commissariat àl'énergie atomique et aux énergies alternatives, CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUEInventors: Cyrille Le Royer, Sorin Cristoloveanu, Jing Wan, Alexander Zaslavsky
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Patent number: 9019760Abstract: A memory device is provided, including a back gate including a first portion of electrically conductive material, a first portion of dielectric material arranged on the back gate, a semiconductor nanobeam arranged on the first portion of dielectric material, a second portion of dielectric material covering the semiconductor nanobeam, a portion of material configured to receive electrons and holes, and configured to store electrical charges and covering the second portion of dielectric material, a third portion of dielectric material covering the portion of material configured to perform storage of electrical charges, and a front gate including a second portion of electrically conductive material covering the third portion of dielectric material.Type: GrantFiled: November 25, 2011Date of Patent: April 28, 2015Assignee: Commissariat a l'energie atomique et aux energies alternativesInventors: Alexandre Hubert, Maryline Bawedin, Sorin Cristoloveanu, Thomas Ernst
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Publication number: 20150061023Abstract: The invention relates to an IC with an electrostatic discharge protection device. There is a buried insulant layer 50 nm or less in thickness and first and second bipolar transistors on the insulant layer, one being an npn transistor and the other a pnp transistor. The base of the first transistor is merged with the collector of the second transistor and the base of the second transistor is merged with the collector of the first transistor. The first and second bipolar transistors are configured to selectively conduct a discharge current between two electrodes of the protection device. There is a first semiconductor ground plane under the insulant layer, being electrically biased, extending until it is plumb with the base of the first bipolar transistor, exhibiting a first type of doping identical to that of the base of the first bipolar transistor with a doping density at least ten times greater.Type: ApplicationFiled: August 4, 2014Publication date: March 5, 2015Inventors: Yohann Solaro, Sorin Cristoloveanu, Claire Fenouillet-Beranger, Pascal Fonteneau
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Patent number: 8634229Abstract: A memory cell is provided with a transistor which includes source and drain electrodes formed in a semiconductor film by respectively N-doped and P-doped areas. The transistor includes first and second devices for generating a potential barrier in the semiconductor film. The two potential barriers are shifted laterally and are opposed to the passage of the charge carriers emitted by the nearest source/drain electrode. One of the devices for generating the potential barrier is electrically connected to the gate. The other of the devices for generating the potential barrier is electrically connected to the counter-electrode. The writing of a high state is carried out by imposing on the P-doped electrode a potential higher than that of the N-doped electrode and charging the capacitor formed between the gate and the semiconductor film. The resetting of the memory cell is obtained by discharging the capacitor.Type: GrantFiled: October 22, 2012Date of Patent: January 21, 2014Assignees: Commissariat a l'Energie Atomique et aux Energies Alternatives, Centre National de Recherche ScientifiqueInventors: Jing Wan, Sorin Cristoloveanu, Cyrille Le Royer, Alexander Zaslavsky
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Publication number: 20140015009Abstract: A tunnel-effect transistor the drain region of which includes a first zone doped with a doping of a first type, and a second zone doped with a doping of a second type forming a junction with the first zone.Type: ApplicationFiled: July 8, 2013Publication date: January 16, 2014Inventors: Cyrille LE ROYER, Sorin Cristoloveanu, Jing Wan, Alexander Zaslavsky
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Patent number: 8581310Abstract: The transistor comprises first and second source/drain electrodes formed in a semiconductor film by N-doped and P-doped areas, respectively. A polarization voltage is applied between the two source/drain electrodes in order to impose to the P-doped electrode a potential higher than that of the N-doped electrode. The transistor comprises first and second devices for generating a potential barrier in the semiconductor film. The two potential barriers are opposed to the passage of the charge carriers emitted by the first and second source/drain electrodes, respectively. The two potential barriers are shifted with respect to an axis connecting the two source/drain electrodes. The two devices for generating a potential barrier are configured to generate a potential barrier having a variable amplitude and it are electrically connected to the gate and to the counter electrode.Type: GrantFiled: September 12, 2012Date of Patent: November 12, 2013Assignees: Commissariat a l'Energie Atomique et aux Energies Alternatives, Centre Nationale de la Recherche ScientifiqueInventors: Jing Wan, Sorin Cristoloveanu, Cyrille Le Royer, Alexander Zaslavsky
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Publication number: 20130069122Abstract: The transistor comprises first and second source/drain electrodes formed in a semiconductor film by N-doped and P-doped areas, respectively. A polarization voltage is applied between the two source/drain electrodes in order to impose to the P-doped electrode a potential higher than that of the N-doped electrode. The transistor comprises first and second devices for generating a potential barrier in the semiconductor film. The two potential barriers are opposed to the passage of the charge carriers emitted by the first and second source/drain electrodes, respectively. The two potential barriers are shifted with respect to an axis connecting the two source/drain electrodes. The two devices for generating a potential barrier are configured to generate a potential barrier having a variable amplitude and it are electrically connected to the gate and to the counter electrode.Type: ApplicationFiled: September 12, 2012Publication date: March 21, 2013Applicants: CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE, COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVESInventors: Jing WAN, Sorin CRISTOLOVEANU, Cyrille LE ROYER, Alexander ZASLAVSKY
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Publication number: 20120134206Abstract: A memory device comprising: a back gate including a first portion of electrically conductive material, a first portion of dielectric material arranged on the back gate, a semiconductor nanobeam arranged on the first portion of dielectric material, a second portion of dielectric material covering the semiconductor nanobeam, a portion of material capable of receiving electrons and holes, and able to perform storage of electrical charges and covering the second portion of dielectric material, a third portion of dielectric material covering the portion of material capable of performing storage of electrical charges, a front gate including a second portion of electrically conductive material covering the third portion of dielectric material.Type: ApplicationFiled: November 25, 2011Publication date: May 31, 2012Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENE. ALT.Inventors: Alexandre Hubert, Maryline Bawedin, Sorin Cristoloveanu, Thomas Ernst
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Patent number: 8010591Abstract: A differential output analog multiplier circuit utilizing four G4-FETs, each source connected to a current source. The four G4-FETs may be grouped into two pairs of two G4-FETs each, where one pair has its drains connected to a load, and the other par has its drains connected to another load. The differential output voltage is taken at the two loads. In one embodiment, for each G4-FET, the first and second junction gates are each connected together, where a first input voltage is applied to the front gates of each pair, and a second input voltage is applied to the first junction gates of each pair. Other embodiments are described and claimed.Type: GrantFiled: May 21, 2007Date of Patent: August 30, 2011Assignee: California Institute of TechnologyInventors: Mohammad M. Mojarradi, Benjamin Blalock, Sorin Cristoloveanu, Suheng Chen, Kerem Akarvardar
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Patent number: 7514964Abstract: An universal and programmable logic gate based on G4-FET technology is disclosed, leading to the design of more efficient logic circuits. A new full adder design based on the G4-FET is also presented. The G4-FET can also function as a unique router device offering coplanar crossing of signal paths that are isolated and perpendicular to one another. This has the potential of overcoming major limitations in VLSI design where complex interconnection schemes have become increasingly problematic.Type: GrantFiled: March 15, 2006Date of Patent: April 7, 2009Assignee: California Institute of TechnologyInventors: Amir Fijany, Farrokh Vatan, Kerem Akarvardar, Benjamin Blalock, Suheng Chen, Sorin Cristoloveanu, Elzbieta Kolawa, Mohammad M. Mojarradi, Nikzad Toomarian
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Publication number: 20080001658Abstract: A differential output analog multiplier circuit utilizing four G4-FETs, each source connected to a current source. The four G4-FETs may be grouped into two pairs of two G4-FETs each, where one pair has its drains connected to a load, and the other par has its drains connected to another load. The differential output voltage is taken at the two loads. In one embodiment, for each G4-FET, the first and second junction gates are each connected together, where a first input voltage is applied to the front gates of each pair, and a second input voltage is applied to the first junction gates of each pair. Other embodiments are described and claimed.Type: ApplicationFiled: May 21, 2007Publication date: January 3, 2008Inventors: Mohammad Mojarradi, Benjamin Blalock, Sorin Cristoloveanu, Suheng Chen, Kerem Akarvardar
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Publication number: 20070008013Abstract: An universal and programmable logic gate based on G4-FET technology is disclosed, leading to the design of more efficient logic circuits. A new full adder design based on the G4-FET is also presented. The G4-FET can also function as a unique router device offering coplanar crossing of signal paths that are isolated and perpendicular to one another. This has the potential of overcoming major limitations in VLSI design where complex interconnection schemes have become increasingly problematic.Type: ApplicationFiled: March 15, 2006Publication date: January 11, 2007Inventors: Amir Fijany, Farrokh Vatan, Kerem Akarvardar, Benjamin Blalock, Suheng Chen, Sorin Cristoloveanu, Elzbieta Kolawa, Mohammad Mojarradi, Nikzad Toomarian
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Patent number: 7158284Abstract: A method for non-invasively probing at least one interface property in a layered structure having at least one interface. In one embodiment, the method includes the steps of exposing the layered structure to an incident photon beam at an incident angle to produce a reflection beam, measuring intensities of the second harmonic generation signals from the reflection beam, and identifying an initial second harmonic generation intensity and a time evolution of second harmonic generation intensity from the measured second harmonic generation intensities so as to determine the at least one interface property of the layered structure.Type: GrantFiled: December 21, 2004Date of Patent: January 2, 2007Assignee: Vanderbilt UniversityInventors: Michael Lee Alles, Norman H. Tolk, Bongim Jun, Robert Pasternak, Ron Schrimpf, Sorin Cristoloveanu
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Publication number: 20060044641Abstract: A method for non-invasively probing at least one interface property in a layered structure having at least one interface. In one embodiment, the method includes the steps of exposing the layered structure to an incident photon beam at an incident angle to produce a reflection beam, measuring intensities of the second harmonic generation signals from the reflection beam, and identifying an initial second harmonic generation intensity and a time evolution of second harmonic generation intensity from the measured second harmonic generation intensities so as to determine the at least one interface property of the layered structure.Type: ApplicationFiled: December 21, 2004Publication date: March 2, 2006Applicant: Vanderbilt UniversityInventors: Michael Alles, Norman Tolk, Bongim Jun, Robert Pasternak, Ron Schrimpf, Sorin Cristoloveanu