Patents by Inventor Sorin Ioan Popa

Sorin Ioan Popa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12352811
    Abstract: A block of circuitry contains at least one sub-block. Test patterns for the sub-block (sub-level test patterns) include sub-level test stimuli and corresponding sub-level test responses. These are ported to the block-level to produce block-level test patterns, block-level test stimuli, and block-level test responses. The block-level test patterns are validated as follows. Propagation of the block-level test stimuli through the block-level design is computed. The signals produced by such computed propagation at the sub-block inputs are compared against the sub-level test stimuli, and the signals produced by such computed propagation at the block outputs are compared against the block-level test responses.
    Type: Grant
    Filed: June 30, 2023
    Date of Patent: July 8, 2025
    Assignee: Synopsys, Inc.
    Inventors: Andrea Costa, Frederic Jean Neuveux, Salvatore Talluto, Sorin Ioan Popa, Leela Krishna Thota
  • Patent number: 11694010
    Abstract: A method includes identifying state holding pipeline stages in a pipeline path of a design for test (DFT) of an integrated circuit design, splitting each pattern of a plurality of patterns into a first part and a second part, reformatting the plurality of patterns to generate another plurality of patterns such that the first part and the second part of each pattern of the plurality patterns are included in different patterns of the another plurality of patterns. The length of the first part is a function of a number of the identified pipeline stages.
    Type: Grant
    Filed: November 3, 2021
    Date of Patent: July 4, 2023
    Assignee: Synopsys, Inc.
    Inventors: Amit Gopal M. Purohit, Sorin Ioan Popa, Denis Martin, Paras Chhabra
  • Publication number: 20220137126
    Abstract: A method includes identifying state holding pipeline stages in a pipeline path of a design for test (DFT) of an integrated circuit design, splitting each pattern of a plurality of patterns into a first part and a second part, reformatting the plurality of patterns to generate another plurality of patterns such that the first part and the second part of each pattern of the plurality patterns are included in different patterns of the another plurality of patterns. The length of the first part is a function of a number of the identified pipeline stages.
    Type: Application
    Filed: November 3, 2021
    Publication date: May 5, 2022
    Inventors: Amit Gopal M. PUROHIT, Sorin Ioan POPA, Denis MARTIN, Paras CHHABRA
  • Patent number: 11036907
    Abstract: Disclosed herein are computer-implemented method, system, and computer-program product (non-transitory computer-readable storage medium) embodiments for automatic test-pattern generation (ATPG) validation. An embodiment includes parsing an ATPG input, semantically analyzing the ATPG input, generating a first HDL model based on the semantic analysis, creating an HDL testbench based on the first HDL model, simulating an ATE test of a circuit structure, and outputting a validation result of the circuit structure, based on the simulating. In some embodiments, the parsing may include lexical and/or syntactic analysis. The HDL model may represent the circuit structure as functionally equivalent to the ATPG input, as determined based on the semantic analysis. In some embodiments, the ATPG input includes a cycle-based test pattern for a first block of the ATPG input, and the HDL testbench includes event-based test patterns that mimic given ATE behavior. The HDL model may be smaller in size than the ATPG input.
    Type: Grant
    Filed: March 2, 2020
    Date of Patent: June 15, 2021
    Assignee: SYNOPSYS, INC.
    Inventors: Slimane Boutobza, Andrea Costa, Sorin Ioan Popa