Abstract: A multi-issue microprocessor selectively assigns, with particular emphasis on an particular type of instruction, in a plurality of instructions to various pipelines. The microprocessor maintains counts of the number of instructions assigned to a first pipeline and a second pipeline. Depending on these counts, the processor assigns instructions of the particular type in the plurality of instructions to the first and second pipelines.

Abstract: A method for handling a conditional move instruction using a two read port per issue slot register file, where the conditional move instruction references a first register, a second register, and a third register is provided. The method involves decoding a conditional move instruction, invoking at least two helper instructions dependent on the decoding, evaluating a register condition of the first register using a first helper instruction, and updating the third register with the contents of either the second register third register dependent on the evaluating using a second helper instruction.

Abstract: A distributed-memory multiprocessor system uses fast and main coherency directories to implement cache coherency. The main directory is stored with user data in main memory and includes sufficient information to determine which memory cells have cached copies of user data stored in main memory. In addition, the main directories specify the states of the cached data. The fast directories cache only some of the main-directory information for only a fraction of the main-memory locations at any given time. The fast directories are tagless in one mode and use partial tags in another mode. The fast-directory information is accessed concurrently with main-directory information in response to data requests. Directory information is retrieved first from the fast directory and is used to launch predictive recalls. Subsequently received main-directory information is used to validate or invalidate the predictive recalls.