Abstract: Described is a monolithic integrated circuit for use in quantum computing based on single and multiple coupled quantum dot electron- and hole-spin qubits monolithically integrated with the mm-wave spin manipulation and readout circuitry in commercial complementary metal-oxide-semiconductor (CMOS) technology. The integrated circuit includes a plurality of n-channel or p-channel metal-oxide-semiconductor field-effect transistor (MOSFET) cascodes each including a single-spin qubit or two coupled quantum dot qubits formed in an undoped semiconductor film adjacent at least one top gate. There is also a back gate formed in a silicon substrate adjacent a buried oxide layer or the at least one top gate, where the back gate controls the electron or hole entanglement and exchange interaction between the two coupled quantum dot qubits. The monolithic integrated circuits described may be used for monolithically integrated semiconductor quantum processors for quantum information processing.

Abstract: Described is a monolithic integrated circuit for use in quantum computing based on single and multiple coupled quantum dot electron- and hole-spin qubits monolithically integrated with the mm-wave spin manipulation and readout circuitry in commercial complementary metal-oxide-semiconductor (CMOS) technology. The integrated circuit includes a plurality of n-channel or p-channel metal-oxide-semiconductor field-effect transistor (MOSFET) cascodes each including a single-spin qubit or two coupled quantum dot qubits formed in an undoped semiconductor film adjacent at least one top gate. There is also a back gate formed in a silicon substrate adjacent a buried oxide layer or the at least one top gate, where the back gate controls the electron or hole entanglement and exchange interaction between the two coupled quantum dot qubits. The monolithic integrated circuits described may be used for monolithically integrated semiconductor quantum processors for quantum information processing.

Abstract: Described is a monolithic integrated circuit for use in quantum computing based on single and multiple coupled quantum dot electron- and hole-spin qubits monolithically integrated with the mm-wave spin manipulation and readout circuitry in commercial complementary metal-oxide-semiconductor (CMOS) technology. The integrated circuit includes a plurality of n-channel or p-channel metal-oxide-semiconductor field-effect transistor (MOSFET) cascodes each including a single-spin qubit or two coupled quantum dot qubits formed in an undoped semiconductor film adjacent at least one top gate. There is also a back gate formed in a silicon substrate adjacent a buried oxide layer or the at least one top gate, where the back gate controls the electron or hole entanglement and exchange interaction between the two coupled quantum dot qubits. The monolithic integrated circuits described may be used for monolithically integrated semiconductor quantum processors for quantum information processing.

Abstract: An embodiment includes a track and hold amplifier device. A device may include an emitter follower transistor coupled to each of an input and an output. The device may also include a charging node coupled between the output and a voltage supply, wherein the charging node is also coupled to the input via the emitter follower transistor. Further, the device may include a cascode switch coupled to each of the input and the output. The cascode switch may be configured to cause the emitter follower transistor to operate in a conductive state and charge the charging node during a track mode. The cascode switch may also be configured to cause the emitter follower transistor to operate in a non-conductive state to isolate the charging node from the input during a hold mode. The cascode switch may include a MOS-HBT transistor combination operating in class AB mode.

Abstract: An embodiment includes an analog-to-digital converter device. A device may include a first track and hold amplifier configured to receive an analog input signal. The device may also include a plurality of paths coupled to an output of the first track and hold amplifier. Each path of the plurality of paths includes a second track and hold amplifier coupled to the first track and hold amplifier, and a successive approximation register analog-to-digital converter coupled to an output of the second track and hold amplifier. The successive-approximation analog-to-digital converter may include heterojunction bipolar transistors, a comparator, R-2R DAC, and a SiGe BiCMOS quasi-CML SAR register and sequencer.

Abstract: An embodiment includes a track and hold amplifier device. A device may include an emitter follower transistor coupled to each of an input and an output. The device may also include a charging node coupled between the output and a voltage supply, wherein the charging node is also coupled to the input via the emitter follower transistor. Further, the device may include a cascode switch coupled to each of the input and the output. The cascode switch may be configured to cause the emitter follower transistor to operate in a conductive state and charge the charging node during a track mode. The cascode switch may also be configured to cause the emitter follower transistor to operate in a non-conductive state to isolate the charging node from the input during a hold mode. The cascode switch may include a MOS-HBT transistor combination operating in class AB mode.

Abstract: An embodiment includes an analog-to-digital converter device. A device may include a first track and hold amplifier configured to receive an analog input signal. The device may also include a plurality of paths coupled to an output of the first track and hold amplifier. Each path of the plurality of paths includes a second track and hold amplifier coupled to the first track and hold amplifier, and a successive approximation register analog-to-digital converter coupled to an output of the second track and hold amplifier. The successive-approximation analog-to-digital converter may include heterojunction bipolar transistors, a comparator, R-2R DAC, and a SiGe BiCMOS quasi-CML SAR register and sequencer.

Abstract: A direct conversion radio frequency (RF) transceiver integrated circuit (IC) is provided. The IC includes a local oscillator block, a receiver block, and a transmitter block disposed on a single silicon-based integrated circuit. Each of such blocks are connected to a ground plane that includes a metal located adjacent to each of such blocks, air gaps located between each section of the metal adjacent to such blocks, each section of the metal being connected to the adjacent section of metal in the group plane at a location on the edge of the ground plan corresponding to a point substantially equidistant from the two sections of metal. A system and method is provided for implementing a direct conversion integrated circuit architecture. A clock distribution system is provided, as well as a method for radio detection and ranging (RADAR) using a Doppler RADAR transceiver system in the W-band. A method for noise isolation between blocks of an integrated circuit is also provided.

Abstract: A method and apparatus for performing image rejection filtering in a radio signal processing device. In a specific example of implementation, the apparatus is a radio transceiver that includes a transmitter and a receiver, each comprising an image rejection filter. A control signal, already available in the usual radio transceiver architecture, is used to simultaneously tune the LO frequency of the transceiver and the image rejection frequency of the image rejection filters. The image rejection filters are designed such that their image reject frequency accurately tracks the Local Oscillator (LO) frequency of the transceiver over a range of frequencies.