Abstract: A digital data buffer has at least one data path and a parallel reference data path. The data path includes a first and second data register, and the reference path includes a third data register. A learn cycle control signal is applied to a multiplexer for selecting between the data path and the reference data path and is also applied in parallel to control circuitry of a phase aligner. The learn cycle control signal is for adjusting the phase of a clock signal at a second clock output of a phase locked loop so as to optimize setup and/or hold timing at the data input of the second data register.

Abstract: A data buffer with a mechanism to optimize the setup/hold timing at the second flip-flop (or data register) so as to reduce the propagation delay time. The data buffer has a data path with a data input for receiving a digital data input signal, a clock input for receiving a clock input signal and a data output providing a digital data output signal for application to a data destination device, e.g. a RAM module in a memory system. The data buffer further has a clock output for providing an output clock signal to the data destination device and a phase locked loop (PLL) with a phase aligner and a first and second data register with respective clock inputs. The data input of the first data register is selectively coupled to the data input of the buffer or to a reference data input through a multiplexer. A reference data path is provided in parallel with the data path including a third data register with a data input to which the reference data input is coupled and a reference data output.