Patents by Inventor Soshi Kuroda

Soshi Kuroda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8629002
    Abstract: To provide a technology capable of preventing the deterioration of the reliability of semiconductor devices caused by the gasification of a part of components of the material constituting a wiring substrate. A wiring layer constituting a circuit pattern is formed over each of the front and rear surfaces of a glass epoxy substrate, and after the formation of a solder resist covering the wiring layer while exposing a part of the wiring layer and prior to a heat treatment (first heat treatment) at 100° C. to 150° C. for dehumidification, a heat treatment (second heat treatment) at 160° C. to 230° C. for gasifying and discharging an organic solvent contained in the material constituting a wiring substrate is performed for the wiring substrate.
    Type: Grant
    Filed: October 26, 2012
    Date of Patent: January 14, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Soshi Kuroda, Masatoshi Yasunaga, Hironori Matsushima, Kenya Hironaga
  • Patent number: 8334172
    Abstract: Technology capable of preventing the deterioration of the reliability of semiconductor devices caused by the gasification of a part of the material constituting a wiring substrate is provided. A wiring layer constituting a circuit pattern is formed over each of the front and rear surfaces of a glass epoxy substrate, and after the formation of a solder resist covering the wiring layer while exposing a part of the wiring layer and prior to a heat treatment (first heat treatment) at 100° C. to 150° C. for dehumidification, a heat treatment (second heat treatment) at 160° C. to 230° C. for gasifying and discharging an organic solvent contained in the material constituting a wiring substrate is performed for the wiring substrate.
    Type: Grant
    Filed: February 9, 2011
    Date of Patent: December 18, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Soshi Kuroda, Masatoshi Yasunaga, Hironori Matsushima, Kenya Hironaga
  • Publication number: 20120061850
    Abstract: To achieve a reduction in cost of a semiconductor device, in a common board (a wiring board), a plurality of bonding leads each extend toward the center of the board, and a solder resist film as a die bonding region supporting a minimum chip is coated with a die bonding material. With this, even when a first semiconductor chip as a large chip is mounted, wire bonding can be performed without causing the die bonding material to cover the bonding leads. Thus, development cost can be reduced to reduce the cost of the semiconductor device (LGA).
    Type: Application
    Filed: September 13, 2011
    Publication date: March 15, 2012
    Inventors: Soshi KURODA, Kenya Hironaga, Hironori Matsushima, Masatoshi Yasunaga, Akira Yamazaki
  • Publication number: 20110201155
    Abstract: To provide a technology capable of preventing the deterioration of the reliability of semiconductor devices caused by the gasification of a part of components of the material constituting a wiring substrate. A wiring layer constituting a circuit pattern is formed over each of the front and rear surfaces of a glass epoxy substrate, and after the formation of a solder resist covering the wiring layer while exposing a part of the wiring layer and prior to a heat treatment (first heat treatment) at 100° C. to 150° C. for dehumidification, a heat treatment (second heat treatment) at 160° C. to 230° C. for gasifying and discharging an organic solvent contained in the material constituting a wiring substrate is performed for the wiring substrate.
    Type: Application
    Filed: February 9, 2011
    Publication date: August 18, 2011
    Inventors: Soshi Kuroda, Masatoshi Yasunaga, Hironori Matsushima, Kenya Hironaga
  • Publication number: 20110074019
    Abstract: To improve reliability of a semiconductor device in which wire bonding using a wire made of copper is performed. A semiconductor device is configured so that one of end parts (wide width part) of a copper wire is joined via a bump on a pad (electrode pad) formed over a main surface (first main surface) of a semiconductor chip of the semiconductor device. The bump is made of gold, which is a metal material having a hardness lower than that of copper, and the width of the bump is narrower than the width of the wide width part of the wire.
    Type: Application
    Filed: September 23, 2010
    Publication date: March 31, 2011
    Inventors: Masatoshi YASUNAGA, Hironori Matsushima, Kenya Hironaga, Soshi Kuroda
  • Publication number: 20100320623
    Abstract: A multi-pin semiconductor device with improved reliability. In a multi-pin BGA, a plurality of wires for electrically coupling a semiconductor chip and a wiring substrate include a plurality of short and thin first wires located in an inner position and a plurality of second wires longer and thicker than the first wires. Since resin flows in from between thin first wires during resin molding, the resin pushes out air, thereby suppressing formation of voids. The reliability of the multi-pin BGA is thus improved.
    Type: Application
    Filed: June 2, 2010
    Publication date: December 23, 2010
    Inventors: Soshi Kuroda, Masatoshi Yasunaga, Hironori Matsushima, Kenya Hironaga
  • Patent number: 7622799
    Abstract: A semiconductor device in which memory chips are stacked on the surface of a wiring substrate has a microcomputer chip and an interposer chip arranged on the surface of the memory chip. The pads of the microcomputer chip and the pads of the interposer chip are arranged almost circularly and are connected by bonding wires.
    Type: Grant
    Filed: December 28, 2006
    Date of Patent: November 24, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Soshi Kuroda, Naoya Yasuda, Hideyuki Arakawa, Akira Yamazaki, Koji Bando
  • Publication number: 20070170573
    Abstract: The semiconductor device with which bonding wires cannot contact easily is offered. In this semiconductor device, memory chips are stacked on the surface of a wiring substrate, a microcomputer chip and an interposer chip are arranged on the surface of the memory chip, and the pad of a microcomputer chip and the pad of an interposer chip arranged almost circularly are connected by a bonding wire. Therefore, since the transfer pressure of liquid resin for sealing can be weakened with a wire, contact of the wires by deformation of a wire can be prevented.
    Type: Application
    Filed: December 28, 2006
    Publication date: July 26, 2007
    Inventors: Soshi KURODA, Naoya Yasuda, Hideyuki Arakawa, Akira Yamazaki, Koji Bando